OOPS that second question should be:
Can I partition the nonce and have each core work on a subset?
Topic: Musing on a new ASIC for Bitcoin Mining - page 2. (Read 1974 times)
OK so while we wait for the physical design guys to get back to me with area and power I'm looking at how to hook up so many cores in parallel.
I have a question or two:
Is there a preferred method of splitting the workload ?
Can I partition the nonce and have each core work and a subset?
Should all cores work on the same job at once?
How do Avalon, BFL and multiple GPUs etc. do it now?
I have a question or two:
Is there a preferred method of splitting the workload ?
Can I partition the nonce and have each core work and a subset?
Should all cores work on the same job at once?
How do Avalon, BFL and multiple GPUs etc. do it now?
Count me in aswell if this will actually count as preorder!
Just imagine what we will be seeing in a few years....
Please let me know how everything goes, I'm certainly interested, and would love to look into buying one or more!
I've been looking at the Bitcoin community for about two weeks now. This started as my company has received numerous requests for an FPGA or ASIC solution for bitcoin mining.
My company is a small design house that primarily designs ASICs, but also some FPGA and PCB level products. We have even done a fair amount of small quantity production. All of our engineers have 20 to 30 years of experience in design and development and we have collectively, successfully completed over 40 ASICs and many FPGAs and system level products. Personally, I am a former VP of engineering for a supercomputer company and an accomplished processor architect.
So just for kicks and chuckles I coded up my own SHA256 engine and built a bitcoin miner. My first effort was to push the design through the Xilinx design tools and see where we stand. I decided to only use the main fabric of the FPGA (no DSP or Block RAM) so that the design will easily translate into an ASIC later. Here are my results:
Xilinx Kintex 7 XC7K160-1 400 MH/s at 10.12 Watts
Xilinx Kintex 7 XC7K160-3 500 MH/s at 9.81 Watts
Those power numbers suggest that I could push the -3 version faster.
Interesting but it seems that the community needs ASICs. So we are doing a trial place and route of this verilog design in our ASIC tools to see where we are with an ASIC.
My company is a small design house that primarily designs ASICs, but also some FPGA and PCB level products. We have even done a fair amount of small quantity production. All of our engineers have 20 to 30 years of experience in design and development and we have collectively, successfully completed over 40 ASICs and many FPGAs and system level products. Personally, I am a former VP of engineering for a supercomputer company and an accomplished processor architect.
So just for kicks and chuckles I coded up my own SHA256 engine and built a bitcoin miner. My first effort was to push the design through the Xilinx design tools and see where we stand. I decided to only use the main fabric of the FPGA (no DSP or Block RAM) so that the design will easily translate into an ASIC later. Here are my results:
Xilinx Kintex 7 XC7K160-1 400 MH/s at 10.12 Watts
Xilinx Kintex 7 XC7K160-3 500 MH/s at 9.81 Watts
Those power numbers suggest that I could push the -3 version faster.
Interesting but it seems that the community needs ASICs. So we are doing a trial place and route of this verilog design in our ASIC tools to see where we are with an ASIC.
+1
(5/5
)
Ok, count me in pre-order list if you make it.
Well I'm encouraged by the interest even if this still in the Newbie area!
The power optimization step is so we can judge how many cores to put on a single chip. You wouldn't want the thing melting after all! This design is mostly flip-flops which use most of the power in a chip so we need to careful here to get it right!
As far as pre-orders go I think we are too early, but assuming this thread persists then I guess an order is established as long as they pay up when required. At least it can be an order for rights of refusal.
The power optimization step is so we can judge how many cores to put on a single chip. You wouldn't want the thing melting after all! This design is mostly flip-flops which use most of the power in a chip so we need to careful here to get it right!
As far as pre-orders go I think we are too early, but assuming this thread persists then I guess an order is established as long as they pay up when required. At least it can be an order for rights of refusal.
if you are working on this, can I suggest you also investigate making scrypt asics and or fpga's too...
you really will get a flood of orders then
you really will get a flood of orders then
sign me up for one asap 
I am also looking for ASIC miner
I am also looking for ASIC miner
This is really interesting, I'll certainly be keeping an eye on this.
add me to the pre-order list as well 
power optimization is truly a secondary concern to most
power optimization is truly a secondary concern to most
BTW, please forget about the power consumption optimization. We need the product first, be it 100w or 500w or whatever. You just need to make the first generation of ASIC miner, sell, ship to us.
Power optimization can be done later in the 2nd gen.
In bitcoin mining, time is truly the money.
Power optimization can be done later in the 2nd gen.
In bitcoin mining, time is truly the money.
It's great new if it's actually true, consider people waiting from BFL for almost one year already with nothing other than "testing", "shipping in two weeks".
I would like to be in your pre-order list too. Please add me.
I would like to be in your pre-order list too. Please add me.
Well trial place and route looks good!!
Timing comes in around 711ps so I'll fudge that to 800ps. So we should get a clock rate of 1.25 GHz. So our core will run at 1.25 GH/s.
So now we will investigate power and area to find the optimal number of cores we can package in a single die (chip)!
I'd like it to be 8 so we have a 10 GH/s chip! 100 chips 1 TH/s
Timing comes in around 711ps so I'll fudge that to 800ps. So we should get a clock rate of 1.25 GHz. So our core will run at 1.25 GH/s.
So now we will investigate power and area to find the optimal number of cores we can package in a single die (chip)!
I'd like it to be 8 so we have a 10 GH/s chip! 100 chips 1 TH/s
It seems that this whole community has been bitten by poor performance from so called ASIC suppliers. I does make me pause to consider if I want to get into this but the potential is intriguing. We certainly know how to build ASICs and assemble them onto boards and manufacture them. We are also hooked up with a number of Contract Manufacturers (CMs) who could manufacture in volume and then build and ship to order.
So I'm going to look into this further and see what happens!
Our trial place and route is nearly done so will post the results shortly!
So I'm going to look into this further and see what happens!
Our trial place and route is nearly done so will post the results shortly!
Sounds great. In case you ever create them, will this post count as a preorder and put me in a good spot to make an early order?
Very cool! Sounds like you guys have a lot of expertise in the area which could make you competitive quickly. Not knowing much about hardware architecture I wonder how this would be scaled to higher speeds. You mention you mostly do small quantity production so you'd probably be thinking of making more powerful more expensive rigs, as opposed to cheaper high volume ~500MH/s USB sticks? Also, are you guys in a position to make the whole product or do you just do integrated circuits?
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