Go learn Verilog, go get a CPLD and implement direct digital synthesis and go implement a SDR and then put it on github.
We are experts with Verilog, CPLD, FPGA, ASIC, SoC design, and how could we help you guys? According to my knowledge, there is no Verilog repo on Github for us to contribute code.
This is an amplitude modulated software defined radio for the whitespace band. 100 Mhz to 700 Mhz carrier. This is the most simple type of radio possible. Its pretty trivial.
Can you hook up an FPGA, maybe one on an ARM development board to an CPLD. We need to take a 600 Mhz to 700 Mhz carrier and amplitude modulate it (multiply the amplitude of the carrier by a value, which changes and can be set). The CPLD needs to implement a Digital to Analog (DAC) converter and then amplitude modulate the carrier. Then this gets amplified and is connected to antenna.
Then we need a Analog to Digital (ADC) implemented on the CPLD for receiving radio on other end. Changing the ADC/DAC 20 million times per second with a 4 to 8 bit ADC/DAC resolution is sufficient for now. A fulll 300 Mhz is ideal, but may not be possible without skillful pipelining.
For example. On beagleboard black, there are ADC/DAC units on the real time units. We can set output to "8" and then voltage level 8 comes out, we feed that into the gate on the amplifier. Then a ~50 Mhz HAM frequency carrier comes in to amplifier and is amplified an amount depending on voltage of gate. Then we change the 8 to a 40. With the real time unit, we can do that ~1 million times per second. Then the value gets amplified, fed into antenna and we are transmitting a sin wave with height 8. We have an array of bytes, one byte is read in a at a time and sets the output value of the DAC, which updates 1 million symbols/second. So we are signaling with radio. This is same thing, except we want the ADC/DAC in the CLPD, so we can do hundreds of MHz and later modulation of the carrier twice per Hz, with changes applied at the zero crossing.
Eventually we want modulation at two symbols per Hz, so 1.4 billion times per second for 700 Mhz carrier (one output for positive part of sin phase and one for the negative phase) with 8 bit resolution for DAC output and +8 bit for ADC reception (or whatever is feasible). The value change for the analog output should occur at the zero crossing of the carrier, to prevent snapping. This will probably require moving the CPLD to ASIC to operate at this baud rate.
At 700 Mhz, with two 8-bit symbols per Hz we are at 11.2 Gb/s for maximum rate (two 8 bit symbols, 700 million times per second). That is the data rate for CPLD to the FPGA. Because of noise, antenna ringing and requirement for forward error correction (100 bits may have to be sent for each received bit), the data throughput may be significantly less than the symbol baud rate. The ASIC version may need a hardware IO protocol (PCIe or other) to interface between the CLPC/ASIC and FPGA at this rate. At those data rates the forwards error correction will need to be implemented in the FPGA, but CLPC prototype may be low enough baud rate for this to be performed in software. We are assuming that directional antennas are used and that the target signal is the loudest signal received, which significantly reduces the resolution requirements on the ADC for reception. Very simple circuit. We are not sure if phase locking or ability to set phase offset is a requirement.
Eventually the FPGA and CPLD, frequency generation and amplifier should be on a single PCB. The FPGA should implement Unipro so we can plug it in into an ARA baseboard. This is the end-target, but prototyping with ARM+FPGA dev board may be easier, or you may have better solution. Alternatively, the first device could be an CLPD + FPGA with a USB interface. Whatever is easier, you probably have a USB FPGA core already. The control board or system should use a Debian linux.
We can provide software in C for an initial forward error correction code. This can be on CPU initially, but move to FPGA is later required to handle full data rates (which may not be hit by the CPLD).
We understand the CPLD can go to 300 Mhz, so 300 MHz modulation of the carrier wave may possible without going to ASICs. Higher frequencies may be possible by including multiple copies of the circuit, with clock skews. For instance, having one DAC for the positive phase and one for the negative phase. A simple CPLD design should be able to achieve a symbol rate of a few dozen Mhz. The ADC needs a floor and max and adjustment to bring the signal within range. This needs to be changed seldom (assume as most 1000 times per second).
I would get it working with a 1-bit or 2-bit ADC/DAC block on the CPLD and then go from there. Alternatively, if there is a very cheap ADC/DAC chip that can handle these ranges or 3 samples per second at 1.4 Ghz, we could use that and wire it into the FPGA. I have feeling that DAC/ADCs chip rated at the required sampling rate are $100 and that getting board down to $20 will require a degree of ASIC integration in the analog frontend.
So the objective here, is to get a lower frequency prototype working in CPLD
- to reduce risk for doing MOSIS/ASIC prototype that can handle full rate and higher resolution in the ADC/DAC. The symbol baud rate for the ASIC version may require integrated hardware IO pin for interface to FPGA, but is otherwise the same.
- then if that works, get a few wafers on an older process
- to have something working early, so that we can distribute dev boards and start on software development and prototyping, antenna development
That is first generation. Second generation
- multiple DAC/ADCs for running multiple antennas
- digital delay line (same signal from each output, but with defined phase shift and amplitude change) so that we can do phased array
- low frequency control or modulation of phase shift (to allow phase locking, reduce interference between transmitters)
- two antennas can resolve or filter on direction from phase shift of signal received by two antennas at a separation.
- N antennas elements each making independent reading of same signal, helps reduce noise floor.
Sorry for late reply cause we are working hard to commit a tape-out due at the end of this Dec.
Thanks for your update and we will try to do some homework and keep you posted.
It will be very helpful if you could release a soft implementation with C on a dev board, and we will look forward to that.
