Topic: The performance claims and prices are unrealistic - page 4. (Read 5319 times)

Nobody designs ASICs by hand just like they don't design FPGA by hand.  They use high level libraries and design tools.  Nobody cares where each individual transistor goes just like a programmer doesn't care which exact memory address every single bit of memory goes.  It is abstracted away.  Comparing these chips to either FPGA or GPU is a false comparison.  These are SHA-256 hashes and will be significantly simpler (and smaller) than any general purpose device like a GPU or FPGA.

Ok.  Now say you had major dollars.  Costing major dollars =/= impossible.

No. You buy existing IP cores from another designer (there's loads out there on offer for SHA-256) then simply pipe and kludge them together.

It's one thing to design processor application, and it is completely different task to actually design the processor.  Something like radeon 6970 gpu has 2.6 billion transistors. For FPGAs like startan-6 we are still talking billions of transistors. For someone starting from scratch, can you imagine how long it would take to draw wiring schematic with a billion components? This is what you would have to do to design a brand spanking new custom ASIC. ASIC is Application Specific Integrated Circuit, so either you have to piece it together via FPGA conversion or you have to design this circuit from scratch. This task would be not easier than it was to design FPGA like SPARTAN-6 in the first place. We talking major dollars here.

I'm pretty sure all Asic "vendors" claimed to not use a fpga2asic conversion but instead a full custom design.

e:fb.

[I split this off the Avalon thread— because it's really nothing to do with Avalon specifically.]


None of the 'asic' vendors are claiming that their next generation products will be FPGA based— all of them have previously shipped FPGA products.  What they're claiming to do is produce custom fixed function mining chips on older processes (65nm for BFL, 110nm for Avalon).  Avalon has even posted a fair amount of their contract information with their foundry.

A miner design is substantially simpler than a FPGA or a general purpose microprocessor, and while fabrication has a high NRE the costs are often overstated. It's possible to do a run in the $100k ballpark on e.g. 130nm, or on better process via an MPW service (although usually this involves long delays). Access to state of the art process is another matter, but for these designs the efficiency gains over FPGA even on an older process can be substantial.

As an aside, MHp_s_/J appears to be confusing power and engery units. You likely want MH/J.

Lets do some basic math:
For existing FPGA design the best can be had is 23MHps/J. There is no reason to anticipate an improvement in FPGA power efficiency, yes, there can be marginal reduction of overhead and the FPGA can be scaled up, but it's efficiency will not increase all that much. Based on existing designs we can anticipate 25MH/J for FPGA. There is nothing special abut ASIC, most ASIC vendors just use a custom programmed FPGA; this is called FPGA to ASIC conversion. So at best ASIC will be 50MHps/J; and i am being VERY generous here. Also, designing a product based on FPGA is one thing, designing an FPGA is completely different. It would take millions of dollars to design a new FPGA.
For the boasted hash rates of 1+GHps we are still talking 25-50 W. This is not unreasonable, until you realize that USB cable provides 5V at 0.5A, which is 2.5W. So those FPGA/ASIC designs better show a mollex connector or something... With single USB you will not hash faster than 2.25/25=0.09GH.

Now lets do some more math:
I work as an electrical engineer and salaries range from $50K/y to $180K/y depending on experience and seniority. To get an FPGA/ASIC project of this scale done you will need 2 very good engineers forking full time for a year. So we talking $200K in salary minimum. You are probably talking closer to $300K in salary by the time you add in customer support, web dev etc. The manufacturers advertise "Limited supply" to not scare miners away. From hardware alone i dont think it is at all possible to make jalapenio for $160, but lets approach this issue from the other end. If they make 10,000 units, the company needs to get $30/unit just to cover bare minimum salaries. Which means all the hardware of something like Jalapeno must cost no more than $119. For this much the best FPGA they can get is like Cyclone III, which does not look cool enough to be beefy enough to do a GH/s. At 315MHz and at least 100 clock cycles per hash (by the time you sync all ins and outs you will waste more, i am being generous here)  we are talking at 3.15 MHps per input path.  Due to the number of available gates just under 200,000 i doubt you can do more than 10 (200,000/256/100=7. hashes in parallel. I am assuming 256 routes per hash since they are 256-bit hashes and 100 gates per hash. So with 3.15MHps*10 we have 31MHps.  In Ideal perfect case, for an FPGA like Cyclone III we are talking (200,00/147,000=1.34) more HPS than from $200 spartan-6. With 100MHps on Spartan6 we would at best get 134MHps on something like Cyclone III, this 134MHps is a theoretical and unattainable number.

Conclusion: All of the FPGA promises are bs for the low prices listed. It is simply not possible to buy enough logic gates for this money to get the advertised MHps.
It would take millions of dollars to design a custom fpga and existing fpgas cost more than any of the advertised prices.