Firstly, don't repeat the propaganda number of "20+%" gain. This is a pure marketing bullshit.
I thought that was more or less established, so I took that for granted. But as I said, my argument was not so much for asic boost by itself (I only looked at the theoretical calculation scheme without imagining that its hardware implementation would be seriously different from the standard way of doing so, as I said, i took that for granted), my argument was this:
"IF you consider asic boost such a phenomenal gain in efficiency that one could call it "an exploit" or "cheating" or whatever, THEN it is entirely wrong to stop miners from using it, because its mere existence lowers PoW security"Note that the "if ... then ..." is also correct when applied to "if false, then false".
This thread was nothing else but a reaction to my argument being censored by people claiming that asic boost is an exploit and should not be used by miners, as it "lowered proof of work". In as much as technically, asic boost is not doing anything, then it is not an exploit, and in as much as it does, then it should be used.
As I said, I took for granted that the gain was of the order of 20%, because that's the amount of raw calculations that one has to do less. I didn't consider that there were technical problems in realizing this, but that doesn't alter the argument that or it is insignificant (and then there's no reason to accuse those trying to implement it to cheat or to exploit) OR it is significant (and then my argument is that it should be used by all means).
Tightly coupling 16 pipelines will greatly reduce the maximum possible clocking rate or lowest possible supply voltage. Additionally the yield of useable chips will be lower. From my general observation of modern semiconductor devices the optimum number of coupled pipelines would be 2,4 or 8, hard to tell. 16 would be past "diminishing returns" and into a "diminishing" territory. I've seen full simulation and analysis made for a different chip (not related to mining) and after doing some substitutions I arrive at the first guess of "-2%", i.e. small loss from synchronous 16-way hashing.
Your argument probably makes sense - as I said, I took the 20% gain for granted and established.
Secondly, by the very fact of using "standard deviation" in you argument you show the depth of your misunderstanding. It is hard for me to guess what you don't understand. My two best guesses are:
1) you may be thinking in terms of some unimodal distributions, where in reality they are always bimodal or multi-modal.
2) you continue to use simplistic textbook statistical models in your estimates. "In statistics, a trial is a single performance of well-defined experiment (Papoulis 1984, p. 25), such as the flipping of a coin,..." This maybe a good approximation of one hashing pipeline pass, where one trial block header is processed in microseconds at the cost of probably nano-dollars. Yet you seem to use it completely exchangeably with chip manufacturing workflow that takes months and costs kilo-dollars or mega-dollars.
I initially thought that your argument was that for two different chip designs with *identical drop out*, as I considered the two designs of comparable difficulty (which, as you line out, may not be the case),
it is not because their dropout percentages are higher than the difference in performance, that this difference in performance is negligible. But this was apparently not the argument you were making, so my "rebuttal" was targetting a mis-understood point (I misunderstood your initial argument).
I didn't realize that the design of an asic boost circuit was more difficult than a design of the normal system, as people were shouting about accusations of a (established, in my mind) 20% increase in efficiency.
The point is that this entire technical hardware discussion doesn't matter for the point I was making: *in as much as* asic boost is any kind of significant boost, it should be used. In as much as it isn't, it is also not "an exploit" "a cheat" or whatever other accusations it took.