Topic: [WIP] Lunch-Box-48 -{small time avalon based miner}- (Read 16911 times)

Well it looks awesome, but far to technical for myself. I would love to see some photos of the finished board and then to see it running when/if you ever get your chips

Because most of the user don't understand your post. Its too technical.
Anyway good luck on your project.
 

Well, regarding the recent developments, I doubt anyone will go for avalon chips now that Bitfury is here and 2nd gen is a few months till shiping.
But this is a hobby project which I intend on finishing, if ever get my 48 chips. 
Anyway, I finished the ASIC board. The schematic pdf, GERBERS and eagle files are on this github.
https://github.com/DaGreatRV/Lunch-Box-48/tree/master/ASIC_board

Why so little activity on this? I had to move into an apartment so I can commute to my new job.

Now I'm going to start on the other PCBs.

So, it's been a while, I've found a job and that frees up a bit of time which I can send on this project.
The design is almost ready, just the bottom side soldermask needs to be edited to allow as much contact with the groundplane to the heatsink.
So here it is. (i'll put some better ones on the git)

http://s22.postimg.org/5p1ogyuq9/ASIC_card_overview.jpg

This has all four layers visible, so it's not that clear. Anyway lets say something about it... It looks like a mess. Which was not unintended.  The parts are in the richt places, switching nodes and inductors are kept away from sensitive bits as much as possible.
The clock lines are very prominent on the toplayer. They get a lot of space, that prevents interference with other parts, also it prevents the line from behaving like a coplaner waveguide, which would mess up my impedance calculations.


http://s21.postimg.org/7andsbvbb/ASIC_card_detail1.jpg

I added footprints for an extra electrolytic cap just in case the ripple on the supply can't be handled by the asics. (C88)
Also R15, the current limit setting resistor might be left out if that function doesn't work well due to a slow rising 12V

More to come...

thx for sharing man , nice work!

Sorry for the lack of recent updates, I've been really busy trying to find a job.
Anyway, I've started a github to share the project files with you.
At the moment I just added the eagle 6 library I created for the ASIC cards/boards.

https://github.com/DaGreatRV/Lunch-Box-48.git

Github does have the nasty tendency to open the library in a text format, as it is XML based.
But you can always copy the text in an empty text file and rename it afterwards.
Or you could download the zip containing the full repository.

Just a small update.
I'm placing and routing the ASIC card. And adding component values in the schematic.
I decided to use buffers for the datalines, just like in the other designs.
I picked this double schmitt trigger part from NXP 74LVC2G17GV, not to expensive, decent specs.
Also for the reset of the ASIC I'll use the STM6780TWB6F voltage monitor from ST. It's cheap, does what it needs to and can be reused for the Controller board.
The original uses an RC delay on the reset, I don't like it personally, not reliable enough, eventhough it would and does work.
 

I've just recieved a sample avalon asic!  

Just to let you guys know what I've been working on lately.
I'm making an Eagle library for the symbols and footprints for the ASIC cards. And I'm pretty far along with that.
After that I'll start working on the layout of those boards.

I've got some pretty cool digital calipers and used those to check part dimensions.
- I noticed that the exposed pad dimensions from the datasheet were correct, not those from the package pdf they added later in their github. 4.7 x 4.7 instead of 5.4 x 5.4
- The contacts wrap around. Sometimes QFN packages just put a marker on the side to indicate a contact location. This is good, it will make handsoldering a whole lot easier

Here is a badly edited and photographed impression of the chip I got.
http://s11.postimg.org/xry5mo1g3/Avalon_ASIC_sample.jpg

Im glad you like it.    I do hope someone will use this to aid in their design.
I know this isn't the easiest subject matter, so I try to be extra verbose in my posts.
But, yeah I know not everyone has a bachelors degree in electrical engineering. And for people who would still like to make electronics despite that, it would be safer to take ready made modules or copy the example from a datasheet.
But for those who like it and are willing to learn, it could be very worth while to design a custom solution.
That takes time, knowledge, insight, experience, intuition and the ability to read datasheets.
But we can all learn. I couldn't even do half the stuff in these posts just a few years ago. 

Been reading each post and I understand maybe 20% of what you are talking about. Perhaps in the future I or someone else will use this as a reference for selecting the components to place on a board. Fun read regardless.

Auxiliary power for the ASIC cards

Ok, so we've got the 1.2V for the asics, now the rest.
I looked at the reference design to see how much current at which voltages would be required.
We need 3,3V for the IO's of the asics and the clock distribution.
And a quiet 1,2V for the PLL's of the asics.

Quiet 1,2V regulator

Lets start with the Quiet 1,2V regulator. The PLL in this chips is not speced, other than the voltage tolerance.
PLL's can be picky eaters, the normal 1,2V, which can be found in this thread, was designed with a larger ripple to improve transient response. The PLL might not like that.
I don't know how much current they'll use so I looked at the reference design where they used a 500mA part for 10 chips. Thus I chose a 600mA pat for my 12 chip board.
Just to be safe. Perhaps it won't need that at all, maybe they just used it because they could reuse it on their controller board.
Yeah, I intend on reusing it aswell on my controller board.

Part chosen: Adjustable LDO AP7165-SPG-13 from Diodes inc. €0,69

Not much to design really with these parts, just a few things to keep in mind.

Transient response, cheap and old parts can be pretty terrible at this, so I pay attention to it. The datasheet checks out, it's not that bad.

Temperature, I will power it with 3,3V so with a 2,1V drop at 600mA you will disapate 1,26W.
I use a SO-8 package with an exposed pad and a pcb with a forced air heatsink cooling. I think it will work out, as the supplier specs it at 40C/W on a 50*50mm board.

PSRR power supply rejection ratio. We are post regulating an SMPS so that is kinda important.
Suppliers almost always show a way to optimistic figure/graph. Not all by the way, more expensive parts, often intended for RF purposes are way better.
Almost all of Analog devices, AMS or expensive ones from Texas instruments and Micrel are pretty good as far as I know.
Anyway lets think about this for a bit.
Most mosfet based LDOs, like this one have, as (most)all mosfets do, a parasitic capacitance from drain to source (drain to bulk and bulk to source in series).
This will allow it to pass high frequency noise.
Also, the regulator feedback loop has a limited bandwidth, it also allows high frequency stuff to pass.
Now the external capacitors will take care of higher frequencies, thus improving PSSR, but due to their construction will start to resemble inductors at higher frequencies.
Thats why I'll put a ferrite bead in series, to get rid of higher frequencies.

For the input and output capacitors I chose a part I used before on this board. The 6,3V 22uF capacitors have about 10uF of capacity at 3,3V and at 1,2V it's 20uF
Parts chosen: 2x 0805 X5R 6,3V 22uF Murata GRM21BR60J226ME39L €0,38 (€0,76)

As for the feedback I chose 31,6K for R2 and 15,8K for R1.
Vout = Vref*(1+(R1/R2))
0,8*(1+(15800/31600)) = 1,2V

Combined cost: €0,69 + €0,76 = €1,45


3,3V supply
I went for a cheap, low power part. I didn't know how much all of this would use, so i picked a 2A part. An smps, because dropping from 12V to 3,3V is kinda wastefull.
Also the manufacturer offers relevant design tools without registering first on their website, a big plus.
It powers the previouly mentioned Quiet 1,2V LDO.
And yeah, I can probably reuse this part for the controller board. For it's 3,3V and the 5V for the USB.
I also aimed to reuse components for different purposes to limit the amount of unique parts.

I went for the AOZ1050PI by Alpha&Omega semi €0,69

Just some comments:
-It's pretty obvious that for their lower end stuff, manufacturers either copy regulators from others, licence a design or codevelop it. It gets rather blatent when the only diffrence is the pinout or the internal mosfets Rds(on). Who am I to judge, they just want to minimize cost on low margin stuff.  
-The part has pretty high Rds(on) mosfets in it, not necessarily a bad thing. That means the switching losses will be lower due to a reduced gate capacitance.
-It is a current mode feedback design which has it's own set of pros and cons, but for this kind of low power part I think it's allright. Remember, that 1,2V 8A regulator from before was voltage mode.
-Because I don't know how much current will be drawn, I should have taken a part with a pulse skipping or other power saving mode. But that could introduce low frequency noise, and I would like this line to be quiet... So I sacrificed light load efficiency for light load noise performance, I hope it's worth it.

http://s14.postimg.org/hoje404gh/example_design_smps.jpg
    
I'm going to stick to the reference design as much as possible. It saves time on a part that is not so critical.

Output voltage
To set the voltage I'll take R1 as 31,6K and R2 as 10k.
Vout = 0,8*(1+(31,6/10)) = 3,33V

Softstart
Damn, it's gonna be emberrassing if I get this wrong. I'll just give it a shot anyway.
In the datasheet the softstart is discribed as a capacitor being charged by a 5uA current source till it reaches 0,8V.
Unlike charging with a voltage source, the voltage will increase in a linear fashion when charged with a current source.
C = (I(t)*t)/V(t)
I(t) is a constant, it won't change over time.
t is the softstart time in seconds. I'll go for 1msec.
V(t) I want it to be 0,8V at 1msec.
(5uA*1msec)/0,8V = 6,25nF   (I'll go with 6,8nF as that is a more common value)

Input capacitor selection
I don't need a lot, there is quite a bit of capacitence on the 12V line on the board. So I'll take two of the previously used 22uF ceramic capacitors.
At that bias voltage I'll be lucky if I have 10uF left with the two of them in parallel.
Input ripple calculation, perhaps useless in this case, but I'll do it anyway.
Vripple_pp = (Iout/(freq*Cin))*(1-(Vout/Vin))*(Vout/Vin)
(2/(500000*(10*10^-6)))*(1-(3,3/12))*(3,3/12) = 80mV ripple

RMS current calculation
Icin_rms = Iout*sqrt((1-(Vout/Vin))*(Vout/Vin))
2*sqrt((1-(3,3/12))*(3,3/12)) = 0,89A
That shouldn't cause more than 1 degree C of temperature rise.

Part chosen: 2x 1210 X7R 25V 22uF TaiyoJuden TMK325B7226MM-TR €0,85 (€1,70)

Inductor selection
The datasheet recommends a 4,7uH part, so lets check it out.
IL_rip_pp = (Vout/(freq*L))*(1-(Vout/Vin))
(3,3/(500000*(4,7*10^-6)))*(1-(3,3/12)) = 1,02A
That is about 50% ripple current, a bit to high in my opinion.
Lets try with 6,8uH.
(3,3/(500000*(6,8*10^-6)))*(1-(3,3/12)) = 0,7A
About 35%, acceptable.
Peak inductor current.
ILpeak = Iout+(IL_rip_pp/2)
2+(0,7/2) = 2,35A (the inductor will have to withstand that current without saturating)

Part chosen: Bourns SRU1048-6R8Y 6,8uH 13,6mOhm 4,1A €0,75

Output capacitor selection
I'll try to reuse the same 6,3V 22uF capacitors used on the 1,2V asic power supply.
At 3,3V three of these will have in parallel about 30uF of capacitence and at worst 2mOhm of ESR.
Output ripple calculation.
Vout_rip_pp = IL_rip_pp*(ESR+(1/(8*freq*Cout)))
0,7*(0,002+(1/(8*500000*(30*10^-6)))) = 7,2mV  (acceptable)

Just to be sure lets check the RMS current.
Icout_rms = IL_rip_pp/sqrt(12)
0,7/sqrt(12) = 0,2A
As expected, nothing to worry about

Parts chosen: 3x 0805 X5R 6,3V 22uF Murata GRM21BR60J226ME39L €0,38 (€1,14)

Feedback loop compensation
As said before this is a (peak)current mode regulator, it measures the current through the top mosfet and looks at the output voltage. Normal current mode will measure over a very small series resistor located after the LC filter. Or a more advanced scheme which measures over the inductor.
Voltage mode only looks at the output voltage. And needs to carry a lot of high frequency signal magnitude back to the feedback node. To react fast to transients.
That means quite a portion of the switching ripple is brought back aswell, which can create bothersome dutycycle jitter or at worst, instability.
One big benefit of (peak)currentmode is that the loop compensation can be simplified, in the voltage mode regulator we had to compensate for the two poles of the output LC filter.
Now the system is reduced to only a pole and a zero. But it's not all good, the pole is output load dependant. Meaning this pole will be all over the place when output current changes.

fp1= 1/(2*pi*Cout*Rload)
Cout = 30uF
A output of 2A equates a Rload of 1,65Ohm --> fp1= 3215Hz
1A -> 3,3Ohm --> fp1= 1607Hz
0,1A -> 33Ohm --> fp1= 161Hz
That sux but we'll deal with it.

The zero lies way up high due to the low ESR.
fz1= 1/(2*pi*Cout*ESR)
fz1= 1/(2*pi*(30*10^-6)*0,002) = 2,65MHz
And that will double if the ESR turns out to be half, that frequency will double.

Using same value components as used before in this design. The 6,8nF capacitor and the 10K resistor used in the output voltage setting.
Lets see if it will result in something acceptable.

It could be my lack of skill, or the guys making the datasheet didn't know either how to properly optimise the feedback loop.
The formullas they use to get the component values keep contradicting themselves, aswell as showing how different the requirements are for different output loads.
A futile exercise, unfortunatly.
So I grabbed the manufacturers spreadsheet to calculate the loop response.
It does not contain this specific part, but the AOZ1022 has an almost identical feedback loop.
So I used that to simulate it and it worked fine with a 6,8nF cap and a 10k resistor even over a wide range of loads.

@2A load
http://s9.postimg.org/c7v2upoxb/3_3_V_Loop_response_2_A.png

@1A load
http://s18.postimg.org/ml59fvwmx/3_3_V_Loop_response_1_A.png

@0,1A load
http://s13.postimg.org/q9z88fw07/3_3_V_Loop_response_0_1_A.png

So, yeah, I'll stick with those values.

Efficiency, for the most part above 90%, only at under 0,5A would you start to see lower efficiencies. I guesstimate.

Combined cost of the major parts: €1,14+€0,75+€1,70+€0,69 = €4,28

To be honest I feel that even the documentation on avalon, the chip and the full system is lacking. But workable non the less, just a bit higher risk.
Those BLF chips sound nice but if there is no documentation whatsoever it's useless to me. I'm not a chinese reverse engineer. 
So documentation should come first before anything.
Also, I am and going to spend quite a bit of time and money on this project. And that is not always so easy as I lost my job a while back. 

Anyway, I hope the people reading this thread will learn something about designing electronics. And if one of you really likes it, you can offer me a job! 

Woosh.... That whole post just went over my head.  I still wish you luck, as I want to see more custom projects done.

http://www.youtube.com/watch?v=UtVx26LlNXA <--- Yifu Guo of Avalon skeptical of Butterfly Labs

Hi DaGreatRV,

I would like to ask for your opinion on BFL offer we got today at https://bitcointalksearch.org/topic/65-nm-chips-bfl-accepted-100-escrow-by-john-k-group-buy-1-kernel32-223571 .

They are willing to sell us (as GroupBuy) advanced 65 nm chips (4 GH/s per piece) on 100% escrow (John K.), on-time-or-deal-is-off policy.

Is developing and producing mining boards capable of running those chips more challenging than for Avalon's 110 nm ones? Would you be interested? (Avalon boards are surely to stay the top priority.)

Since, I'm refining the deal right now, I can use any suggestions about documentation, sample chips etc. I should require for you/other developers as part of the deal.

Thank you.

Clock distribution for the ASIC cards

UPDATE: I chose a third option, a cheaper one. See end of this post

So now I've taken a look at the distribution of the clock. A few things were clear from the start. I like well terminated clock lines, low EMI and low cost.
I also like a clean clock edge transition between 0,8V and 2,0V (traditional 3,3V cmos thresholds). If it's not, an extra, narrow, pulse could be sent to the ASIC, which would not be nice to it's PLL.
Also fast edges tend to decrease jitter, but fast edges mean you'll get issues with reflections on your transmission lines. No idea if the avalon clock input has a shmitt trigger input.
Also, no layer changes, vias represent an impedence change. Which can cause increased reflections and extra EMI.
Anyway, I've narrowed it down to two setups.

The first shows a single clock source which via a 1:3 fanout buffer sends it to logic buffers with shmitt trigger inputs located near every asic.
Those three fanout lines are daisychained without(with minimal) stubs and is terminated by an RC network.

http://s10.postimg.org/mnua5f1mh/clocknet_daisy_chained_RCterm.jpg
thousand hours in paint.net

I've done some simulations in LTspice to estimate how the clock would look like at the end.
I take 0,3nsec as the worst(fastest) case rise time, as many manufacturers ony talk about typical or maximum rise/fall times. Understandable, as that constrains the usable frequency range.
But for me, wanting to limit reflections, I want a buffer that is just fast enough to retain a decent puls form.
I've simulated the daisychain by seperating the transmission line with capasitors, representing the input pads of the buffers.
Distance is set by the propagation delay of the line, according to my calculator a 75Ohm line delays about 56psec per centimeter.
I always used 50psec per centimeter as a rule of thumb.
To take account for process variations I did three simulations with varying output imedances and line impedances.

The pictures are clickable.
http://s2.postimg.org/l93i3tcr9/Sim_parallel_RCterm_daisychain_normal.jpg  
Normal condition, well matched impedance

http://s7.postimg.org/ah24l3qp3/Sim_parallel_RCterm_daisychain_upper_worst.jpg
Worst case high impedance.

http://s15.postimg.org/eiv91plmf/Sim_parallel_RCterm_daisychain_lower_worst.jpg
Worst case low impedance.

I'm not to happy with that, the position closest to the source doesn't transfer the 0,8V to 2,0 and back, too well.

_______________________________________________________________________________ _______________________________________________________________

Now to the second part, point to point connections. A single clock goes to a single, 1:12 fanout buffer, which sends a dedicated clock line per asic across the board.
They also have a resistor near the source to terminate the line. Rdriver+Rseries = Zline in an ideal world.

http://s7.postimg.org/6gm90r2ej/clocknet_fanout_point_to_point.jpg
I left out the series resistors.

I simulated the point to point connection, the resistor at the end reprisents the input resistance(resulting in leakage current) of the clock input of ASIC.
The capacitors represent parasitics of the pads, the chips are located on.
I used a 1nsec delay, which is about 20cm in length, while in reality we'll probably end up at half of that as a maximum.

The pictures are clickable.
http://s12.postimg.org/4qzvu3h2x/Sim_series_Rterm_pointtopoint_normal.jpg
Normal, well matched.

http://s10.postimg.org/sc11fomwl/Sim_series_Rterm_pointtopoint_upper_worst.jpg
Worst case high impedence.

http://s23.postimg.org/ehrn43p7b/Sim_series_Rterm_pointtopoint_lower_worst.jpg
Worst case low impedance.

While not perfect, the 0,8V to 2,0V and back transition looks way better. But routing all those lines might make routing the 1,2V connections more difficult.
Also there is probably increased EMI.


Conclusion: I'll pick the second, point to point solution. Even with it's drawbacks it delivers a more robust connection. And that was my main priority.

Parts chosen:
13x generic 1% 0603 resistors of 37Ohm
Oscillator: CTS CB3LV-3C-32M0000 (it's a bit large, but it's the cheapest I could find, so whatever)
Fanout 1:12 buffer: texas instruments CDCLVC1112PWR, A bit overkill in the frequency department, but it keeps averything on one chip, that's what I was going for.
Combined price, around €6 to €7. Perhaps I could find a cheaper fanout buffer.  

_______________________________________________________________________________ _______________________________________________________________

UPDATE:
I was not happy with the cost so I chose some alternatives. It did require a second chip though.

http://s11.postimg.org/hsl274aab/clocknet_fanout_point_to_point_2.jpg

Parts chosen:
1x Oscillator CTS CB3LV-3C-32M0000 (no need to change it) €1,14
1x Fanout buffer 1:10 Pericom PI49FCT3807CQE (old and cheap, but for these frequencies it's good) €1,16
1x Fanout buffer 1:4 OnSemi NB3N551DG (a bit better and more expensive, but more energy efficient and saves board space)  €1,57
13x generic 1% 0603 resistors of 59Ohm (higher value than befor due to the lower output impedance) €cheap

So we'll end up cheaper, like at €4 or so.

These buffers have individually specified Vout_high and Vout_low voltages at a certain current. From there a output impedance could be calculated.
Typical of these CMOS outputs (pmos/nmos totem pole) the Vout_high has a higher impedance than the Vout_low. This makes finding a proper termination more difficult.
The low to high edge has a diffrent output impedance than the high to low edge. I couldn't recreate that quickly in ltspice, so in the end I ran it all twice, changing the impedance.
59Ohm is a bit to high, but provides a safety margin in case the trace impedance turns out quite a bit higher than expected.

Please keep in mind that these simulations only show one edge correctly.

http://s24.postimg.org/abh3b22jl/Sim_series_Rterm_high_to_low_high_imp.jpg
High to low edge, high trace impedance.

http://s21.postimg.org/g8mra4l03/Sim_series_Rterm_high_to_low_low_imp.jpg
High to low edge, low trace impedance.

http://s10.postimg.org/3tm25l5o5/Sim_series_Rterm_low_to_high_high_imp.jpg
Low to high edge, high trace impedance.

http://s24.postimg.org/lkdnht9wh/Sim_series_Rterm_low_to_high_low_imp.jpg
Low to high edge, low trace impedance.
 



 

SMPS design for the asic cards
Welcome to the land of never ending tradeoffs, designing an SMPS. Choices effect parts of your design in unforseen ways.
Saving cost at one place increases cost somewhere else, same goes for efficency, transient response, ripple supression, etc... I'll try to find an optimum.
I maintain a maximum component hight of 10mm to allow space between ASIC cards. This will constrain filter component choice.
Why go through all this effort? Because I'm an EE and I like it.  


Controller intersil isl6545   €2,40   
Why this one?
It's cheap, runs at 300KHz and drives with the full vcc(12V) instead of a 5V from an internal LDO.
I go for low frequency because I assume that is best for these high current designs. The overall solution size will increase.
Stuff to calculate/pick:
Mosfets, output inductor, input and output capacitor, feedback, compensation and overcurrent protection.


Mosfet selection
I'll go for the Alpha and omega dual asymetric nmos line. Why this brand? It's cheap and well speced.
Why Asymetric? Top and bottom mosfets have diffrent requirements. Especially at low dutycycles. We're at 10%. (!)
The topfet(Q1) needs to switch fast, thus benefitting more from a low gate charge than lower Rds(on).
The lowerfet(Q2) conducts for 90% of the time, thus benifitting greatly from a lower Rds(on).
I'm going to use the 10Vgs Rds(on) values. That aproximates worst case for 12Vgs and allows for some margin.
I compared two, one with lower gate charge in the bottom mosfet than the other. Top fets are almost identical. Does the reduced Rds(on) wheigh up to the increased driver losses? And can the driver handle the extra dissapation?
Don't be mislead by gate capacitance values in datasheets, they are not fit for this calculation. (They specify at 0 Vgs)
I'm going to look at the Vgs to Qgate (Qtotal) graph and extrapolate the gate charge at 12V.  

AON6973A - €0,86
Q1_Rds(on) = 4,3mOhm
Q2_Rds(on) = 3,1mOhm
extrapolated_Qgate(Q1) = 20nC
Cgate(Q1)=Qtotal/Vgate = 1,66667nF
extrapolated_Qgate(Q2) = 35nC
Cgate(Q2)=Qtotal/Vgate = 2,91667nF
Pdriver = Cgate*Vgate^2 * freq (300kHz)
Power disapation driver combined Q1 and Q2 = 0,072 + 0,126 = 0,198W
Power used to charge gates = 0,5*0,198W = 0,099W
thermal resistance driver=98degC/W
98*0,198 = 19,4 degrees C above ambient. (temperature rise in driver)
At one tau time the gates are at 63% enough to fully switch on. Switch off will take longer due to the low Vth spec. I go for three tau times.  
Rgate+Rdriver=R
R(Q1) -> 1,5+3,0 = 4,5Ohm
R(Q2) -> 1,5+2,4 = 3,9Ohm
Q1(switch)time = 4,5*1,66667*10^-9 = 7,5nsec (switch off 22,5nsec)    
Q2(switch)time = 3,9*2,91667*10^-9 = 11,4nsec (switch off 34,2nsec)
top MOSFET loss approximation: P(Q1)=Iout^2*Rds(on)*D+(0,5*Iout)*Vin*tsw*freq
bottom MOSFET loss approximation: P(Q2)=Iout^2*Rds(on)*(1-D)
Iout = 8A
D = 0,1 (1,2/12)
tsw = switch on + off time
P(Q1)= 0,46W
P(Q2)= 0,22W
Ploss(fet+drv) = P(Q1) + P(Q2) + P(drv) = 0,46 + 0,22 + 0,198 = 0,878W

AON6932 - €1,00
Q1_Rds(on) = 4,1mOhm
Q2_Rds(on) = 1,7mOhm
extrapolated_Qgate(Q1) = 19nC
Cgate(Q1)=Qtotal/Vgate = 1,58333nF
extrapolated_Qgate(Q2) = 64nC
Cgate(Q2)=Qtotal/Vgate = 5.33333nF
Pdriver = Cgate*Vgate^2 * freq (300kHz)
Power disapation driver combined Q1 and Q2 = 0,068 + 0,23 = 0,288W   = P(drv)
Power used to charge gates = 0,5*0,288W = 0,144W
thermal resistance driver=98degC/W
98*0,288 = 28,2 degrees C above ambient. (temperature rise in driver)
At one tau time the gates are at 63% enough to fully switch on. Switch off will take longer due to the (very)low Vth spec. I go for three tau times.
Rgate+Rdriver=R
R(Q1) -> 1,5+3,0 = 4,5Ohm
R(Q2) -> 0,7+2,4 = 3,1Ohm
Q1(switch)time = 4,5*1,58333*10^-9 = 7,1nsec (switch off 21,4nsec)
Q2(switch)time = 3,1*5.33333*10^-9 = 16,5nsec (switch off 49,6nsec) <- (I don't like this long switchoff time)
top MOSFET loss approximation: P(Q1)=Iout^2*Rds(on)*D+(0,5*Iout)*Vin*tsw*freq
bottom MOSFET loss approximation: P(Q2)=Iout^2*Rds(on)*(1-D)
Iout = 8A
D = 0,1 (1,2/12)
tsw = switch on + off time
P(Q1)= 0,43W
P(Q2)= 0,18W
Ploss(fet+drv) = P(Q1) + P(Q2) + P(drv) = 0,43 + 0,18 + 0,288 = 0,898W

Conclusion: I pick the AON6973A. It's cheaper and at 8A output it results in a more efficient solution.
Note: Iout is squared in those formullae, a calculation for a somewhat higher current would tip the scales the other way.


Inductor selection
A pretty expensive part, but worth it if done right.
The standard way to pick one is to chose a ripple current you are willing to tolerate. I will tolerate a 30 to 40% ripple current.
That is pretty high, but in this case the application constantly uses a pretty high current, so low current efficiency is not that important. This does require a larger output capacitance.
L=(Vout*(Vin-Vout))/(Vin*freq*ripple_%*Iout(max))
(1,2*(12-1,2))/(12*300000*8*0,3) = 1,5uH   (for 40% -> 1,125uH)

Chosen: Epcos B82559A0142A013 1,4uH 1,5mOhm 22A(Isat) €2,50 ~ €3,00

Ilpp = (1,2*(12-1,2))/(12*300000*(1,4*10^-6)) = 2,6A
Ilpeak = 8 + (0,5*2,6) = 9,3A
Il(RMS) = sqrt(Iout^2+(Ilpp^2)/12) = 8,03A

Worse case inductor temperature is, I guess 60degC or so. (guesswork!)
Rwire = 1,5mOhm * (1+0,0042*(60deg-20deg)) = 1,75mOhm
Pinductor(cu) = 8,03^2 * 1,75m = 0,113W

Conclusion: The inductor wire resistance is the biggest loss factor in the inductor at higher currents. Small loss compared to the mosfets and their driver.


Output capacitor selection
There is only 1,2V at the output, so very low voltag capacitors can be chosen.
maximum ESR? It's primary cause of voltage ripple by absorbing the inductor peak to peak current.
Lets go for 24mV p-p
Ilripple (pp) = 2,6A
ESR<0,024/2,6 = 9,23mOhm  (we'll manage)
I'll go for 2,5V nichicon caps, they have low ESR, they are cheap and next to that some small X5R caps to do the high frequency stuff.
Part chosen: Nichicon RHA0E821MCN1GS 2,5V 820uF 8mOhm 4,5AIrms €0,84
For high frequency 2x 0805 X5R 6,3V 22uF Murata GRM21BR60J226ME39L €0,38 (€0,76)
For really high freq spikes 1x 0306(reverse geometry) X5R 6,3V 4,7uF TaiyoJuden JWK107BJ475MV-T €0,53
Total = €2,13

Vout ripple(pp) = sqrt((2,6/((820*10^-6)*8*300000))^2 + (2,6*0,008)^2) = 20,8mV(pp)
How does this act during a load step? I would like a maximum voltage change of 50mV at a load step of 8A.
Estimate calculation: Cout(min)=(Istep^2*L)/(2*Vout*Vchange)= 747uF  (we are allready over this)
The small inductance reduces the capacitance need for transient supression.

Icout(rms) = 2,6/sqrt(12) = 0,75A    (way below the allowed 4,5A)
Pdiss(cout) = 0,75^2 * 0,008 = 0,0045W  (negligible compared to the rest)


Input capacitor selection
Has to be able to handle the input voltage, load steps on the output. Reduce ripple on the 12V line.
Estimate for the required RMS current of the input capacitor.
Iincap(rms)=(Iout/Vin)*sqrt(Vout*(Vin-Vout))
(8/12)*sqrt(1,2*(12-1,2))=2,4A = Iincap(rms)

Minimum capcacitance for a certain ripple: (I chose 25mV)
Cin(min)=Iout*(D*(1-D)/(Vpp*freq))
8*(0,1*(1-0,1)/(0,025*300000)) = 96uF (seems a bit low)
Now take a formulla which factors in the esr with that ripple requirement.
I chose a 150uF 22mOhm capacitor to calculate (first with two, then three in parallel)
Vpp(esr)=esr*(Iout+(1/(2*freq*L))*D*(Vin-Vout)) ->102mV(x2cap) -> 68mV(x3cap)
Now for capcitance there are two formullas to do.
if 1<(Vout^2)/(2*freq*L*Iout-D*(Vin-Vout)) solve: Vpp(cap)=(1/(8*L))*((Vin-Vout)/(Cin*(Vin^2)))*(2*L*Iout+(Vout/freq))^2
if 1>(Vout^2)/(2*freq*L*Iout-D*(Vin-Vout)) solve: Vpp(cap)=(Iout*Vout*(Vin-Vout))/(freq*Cin*(Vin^2))
The first equation was smaller than 1 (=0,255)
So I solved Vpp(cap)=(Iout*Vout*(Vin-Vout))/(freq*Cin*(Vin^2)) -> 8mV(x2cap) -> 5,3mV(x3cap)
It is clear that the ESR has the largest influence on the input ripple.

Parts chosen: 3x Nichicon RHA1C151MCN1GS 16V 150uF 22mOhm €0,90 (€2,70)
For high frequency: 1210 X7R 25V 22uF TaiyoJuden TMK325B7226MM-TR (€0,85)
TaiyoJuden TMK107ABJ225KA-T (€0,23)
Total = €3,78

Do note that these 450uF*12=5400uF are all attached to the PSU and the supplier does not specify a maximum startup capacitance.
But it is a fairly modern PSU, perhaps it will be no issue.

Power loss input cap:
Pdiss(cin)=Iincap(rms)^2 *esr -> 2,4^2*0,0073 = 0,042W

Estimated efficiency at 8A output current: (worst case)
Ploss(total)=Pdiss(cin)+Pdiss(cout)+Pinductor(cu)+Ploss(fet+drv) = 0,042+0,0045+0,113+0,878 = 1,038W
Pload = 1,2V*8A = 9,6W
Pinput = Ploss(total)+Pload = 1,038+9,6 = 10,638W
efficiëncy = Pload/Pinput = 9,6/10,638 = 90,24%    (not bad)  

Room for improvement? Most losses are located at the mosfets and the driver. Cost spent there might be most effective.

Solution cost: €12,17    (pretty expensive, but worth it, I hope)

Overcurrent protection
Rocset is attached to the lower drive output. The value is measured by the controller at startup.
It will trip at a set peak inductor current.
Ipeak=(2*Iocset*Rocset)/Rds(on)
Iocset(min) = 19,5uA
Rds(on)@125C = 5,3mOhm
Ipeak = 10A  (safe value)
Rocset = (Rds(on)*Ipeak)/(2*Iocset) = 1359Ohm (rounded to practical value, 1k5 1%)

Output voltage set (feedback)
The output voltage is twice the Vref, so Rs and Ro are equal.
Rs is the top resistor
Ro is the bottom resistor
Vref = 0,6V
Vout = 1,2V
Ro = (Rs*0,6V)/(Vout-0,6V)
I chose 3,3KOhm for both

Feedback compensation
Our controller has to respond quickly to transient loads, but should at the same time be immune to the switching ripple and should be slower than the output filter to prevent all kinds of bad mojo. ie. phase margin above 45deg at 0dB to be safe.

http://s13.postimg.org/zf2t2dth3/smps_feedback_comp.jpg
That is how it looks like, now to determin the component values. I'll just follow the datasheet guidelines as they probably know their part best. I still should try to simulate the bode(gain/phase) plot in matlab or whatever.  
3db freq lc filter 1/(2*pi*sqrt(1,4uH*820uF)) = 4,7kHz =Flc
3db freq cap+esr filter 1/(2*pi*820uF*8mOhm) = 24,2kHz = Fce
R1 = 3,3kOhm
F0 = 60000Hz (0,2*300000) (safe distance from the switching frequency)
d(max) = 1 (duty cycle in this convertor can go to 100%)
Vosc = 1,5V (typical value)
R2 = (Vosc*R1*F0)/(d(max)*Vin*Flc) = 5266Ohm -> 5230Ohm is the closest E96 value
I'm going to place the zero (Fz1) a bit lower than usual because of the high Fce/Flc factor. (quality factor)
C1=1/(2*pi*R2*0,25*Flc)= 25,9nF -> 22nF ( common value )
The Fp1 pole should lie at Fce.
C2=C1/((2*pi*R2*C1*Fce)-1)= 1,33nF -> 1,3nF is a regular value
Place zero Fz2 at Flc
R3=R1/((Fsw/Flc)-1) = 52,5Ohm -> 52,3Ohm chosen
Place pole Fp2 at between 0,5 to 1,0 the Fsw. I'll try first at 0,7 and pick the closest real value and check where we ended up.
C3=1/(2*pi*R3*0,7*Fsw) = 14,5nF -> 15nF is normal. (we ended up at about 0,68*Fsw)

So I simulated that in the webbased software of the supplier of the controller.
First theoretical:
http://s15.postimg.org/72gwz718r/Loop_response_theoretical.jpg
Looks fine, the margin is nearly 60degrees.

Now a simulation of the whole system:
http://s12.postimg.org/ips1gp90d/loop_response_simulation.jpg

A somewhat higher 0dB crossover at 74KHz and a lower margin at 54 degrees.
I'm satisfied with that. This system will be able to handle extreme transients. And all that for sacrificing some ripple suppression. Worth it.

tl;dr this smps is awesome

If you manage to get this working I would absolutely be willing to send you 48 chips and enough FIAT to purchase, assemble, ship and profit off this design.

I will put you into the devlist in my sig then. As provider of a open source miner blueprint. If you dont want let me know.

I'll share the eagle design files and GERBERs. Also other stuff needed to replicate it. This is a hobby project, I don't intend to produce boards or kits, whatever.
Oh, and when I have components and/or boards to show I will post some pictures.

Watching. Be interesting to see peeps custom cases further down the line.

Do you mean you will show a design blueprint here one day or do you offer something other like assembly, diy-kits or similar?

What is the purpose of this thread?
Documenting and sharing my work on an Avalon based miner. Including design choices and the reasons for them.
Ofcourse you are free to point and laugh, but please post your reasons, I might learn something.

Can I use your designs?
Yes you can, though I would like to be credited.

Sounds easy, and FREE! What's the catch?
If you want to sell products based on my design, I'll give an address where you can donate.

I want to see 3d pictures of your design!
I can't promise sketchup pictures, I need more training to use it properly.

Okay, get to it then.
I'm already at it. Some stuff is not that far along, so that will be a bit empty for the time being. This post is a work in progress as well.  

Edit:
Here is the link to Github of this project

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Lunch-Box-48

Conception
I bought 48 avalon chips in t13hydra's groupbuy and I have to put them somewhere to work in 8 to 10 weeks. Klondike and BitBurner are fun designs, but I'm an engineer, I want to design my own boards.
I wanted to stay as compatible to the regular avalon rig as possible. Though cgminer would have to start with another flag, "--avalon-options 115200:24:10:45:282" is the default. I hope the current firmware accepts changes to the second and third number. Ending up at something like this: "--avalon-options 115200:12:4:45:282".
So I'll be using the FPGA and wr703n.

What's in a name
I was looking for a name, but at first ended up a 'cherry island', Avalon could mean 'Apple island' according to wikipedia. So a cherry is a smaller fruit than an apple, you get the picture...
But looking at the enclosure I chose, it kinda reminded me of an oversized lunch box. Adding the number 48 is simply a reference to the number of avalon chips.

Design method
Schematic design and PCB layouting are my strong points. I also do some VHDL and C. I like FPGA's, to bad the Avalon team can't publish the VHDL yet as there is some proprietry stuff in there. So I'll be forced to use their bitstream for the BGA packaged FPGA, If I had the VHDL I could trim out a lot of excess IO's so I could migrate to a TQFP-144 package. I love handsoldering those.
Anyway, I work from the outside in. Starting at the enclosure, to module placement, to board design and cabling.
The work is divided in different sections, the enclosure as the top level, the boards are the sublevels. I will discuss these seperatly and ad my thoughts, concerns, ideas, doubts, etc..

Design tree
Enclosure->
                -> tl-wr703n
                -> Controller board
                -> ASIC cards
                -> Connector board

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Enclosure

Hammond 1402K has got about 230x238x93mm internal space. Aluminum. pdf
PSU 150W open frame 12V 91~93% efficiëncy. Type: Iccnexergy FSA150012A. pdf
 - A bit expensive but has high power density (watt per cm³) 127.0mm x 76.2mm x 30.9mm
Decent power entry, a combination of socket, fuse and switch would be good, I think. 06A2D by Delta electronics link
two fans attached to front panel, if they fit, pick 92mm, else 80mm. Mechanical vibration could be problematic in this enclosure. (add fanfilters)
modify front and back panel with a multitool(dremel).
Controller board
Connector board
four ASIC cards
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tl-wr703n

I need a modified tl-wr703n to run the standard Avalon firmware.
- I can buy a premodified one on ebay. It has the 64MB RAM chip. link
I still need to modify it so it can be powered from the device side. According to the wiki I should populate R113 with a 0R resistor to do it.
Also an external antenna is preferable, so an SMA connector mod needs to be done aswell. Several distributors offer chassis mounted SMA connectors wth a cable already attached to it, quite handy. ebay
- I've got a metal enclosure, should the antenna ground/shield be electrically connected to it? Yes (tentative)
A 9dBi antenna would be nice, doesn't seem to use the 5.8GHz band, so the antenna doesn't need to be specified for that. Example ebay
38cm is a bit long, perhaps I won't need all that gain? 7dBi is 19,5cm.

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Controller board
Designed to be ordered at PCBpool.
4layer with decent specs to fully break out the 256bga FPGA package.
Stackup:
l1          0,018mm
prepreg  0,38mm
l2          0,035mm
core      0,71mm
l3          0,035mm
prepreg  0,38mm
l4          0,018mm
Based on the reference design. Aiming for about 80x80mm size.

Separate board which could be replaced with a cheaper one when the VHDL becomes opensource.
- Is the HUB chip necissary? tl-wr703n has USB issues, perhaps they are solved by this? Not sure yet. Gonna place it anyway.
- Connect all the data lines to the connectors? We could save space and time. But future modifications might need more data channels. Not sure yet.
- Can the current bitstream handle unconnected datalines? external pullups for the unused report lines? Yes it can, as you can run the original with fewer modules.
- Needs one temp sensor on board and the other on a heatsink. Temp sensor 1 is on the board, Temp sensor 2 or 3 could be used for the heatsink. 3 is standard.
- Connect the two fans to FAN2 and FAN3
- Replace the fuse with an active current limiting chip on the USB B port connected to the tl-wr703n. Do the same with the downstram facing port of the hub.
- Reuse the powersupply designs from the ASIC cards for the 5V, 3,3V and 1,2V nets.
- As a connector use a straddle mount pci-express socket (4x) with 64 contacts.
- Use a voltage supervisor to handle the reset of the FPGA. STM6780TWB6F or similar. Instead of the standard RC network

Needs reflow soldering due to BGA package. Perhaps let someone else do it, or make/buy a reflow oven. (not sure yet)
- I've got a quote to have the FPGA mounted on two boards, cost €25 excluding shipping. (I asked for two boards cause i like to keep a backup board just in case)
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ASIC cards
Designed to be ordered at Seeedstudios. 4layer 70x180mm
Stackup:
l1          0,035mm
prepreg  0,2mm
l2          0,018mm
core      1,2mm
l3          0,018mm
prepreg  0,2mm
l4          0,035mm

12 avalon chips per card, a 12V to 1,2V dc/dc smps per four chips.
There are three cheap standard 1/2brick sized heatsinks per card, each covering 4 avalons and it's smps. Heatsinks are about 60x60x25mm. Type 518-95AB by Wakefield.
PCI-express card edge connector is used for availability and cost.
    - v-scoring board edges? Not necessary (tentative)
    - locking cards in place? Standard board locks dont secure all angles. Perhaps a screw connection to secure them. Chose to go with simple scewable brackets to crew the cards onto the connector board.
Clock distribution. One 32MHz crystal ocillator outputting 3,3V CMOS. Going to a clock buffer/splitter, with high rise and fall times, to go to the three groups of 4 chips.
Those chips in a group will have their clock daisychained and terminated at the most remote point with an RC parallel termination. Need to properly caculate that.
- Think about layer use. Perhaps l1 = power, l2 = GND, l3 = data and clock, l4 = GND
Ground the heatsinks, or let them float? Float, to prevent RF current flow in the heatsink. (tentative)
Select a buck convertor that can supply 2A at 1,2V to each avalon chip.
Chip footprint conflict. Two documents in the avalon-ref github specify different pad sizes. The footprint from the datasheet was correct.
- Use a voltage supervisor to handle the reset of the ASIC. STM6780TWB6F or similar. Instead of the standard RC network

Update: SMPS designed, 90% efficiency Link to calculations

Update: Clock distribution designed. Went for a point to point solution in the end. Link to simulations

Update: I revised the clock distribution, while still point to point, it now uses cheaper parts.

Update: The auxiliary power supplies are designed and can be reused on the controller board. Link to post
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Connector board
Designed to be ordered at Seeedstudios. 2layer 100x150mm (prelim)

A simple board which connects the controller board to the ASIC cards and to the PSU
Has four pci express connectors for the ASIC cards.
Connectors for the 12V
A connector for the controller board, not sure which one(s). Depends on the number of signals.
There are 24 lines going to the ASIC boards and 24 comming back. 48 in total.
I chose a straddle mount pci express x4 socket, that has 64 contacts. Surplus can be used for power.
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