Re: Zcash Equihash PoW Releasedhttps://z.cash/blog/why-equihash.htmlWell some Monero folks seem to very interested, so I decided to take a look because I suddenly remembered something from Iota's whitepaper:
http://188.138.57.93/tangle.pdf#page=20 (4.3 Resistance to quantum computations)
If you look on page 115 of Bernstein's Post Quantum Cryptography, it confirms a sqrt(N) speedup for Wagner's solution to the Generalized Birthday Problem for the hypothetical quantum computer. So if Equihash is using a large list of values to be sorted, then the speedup could be so great that a quantum computer could rewrite the entire block chain quite easily by redoing the past proof-of-work exponentially faster than it was originally done.
It appears that a memory hard algorithm such as Cryptonite would not have this problem.
I am just rushing and have not reread the Equihash white paper carefully, so I may have a mistake in my analysis.
Additionally I was thinking that this Equihash can be trivially sped up on an ASIC because the Equihash algorithm is not memory latency bound and thus is bound on the sorting and computation speed and/or the memory bandwidth, which can be optimized with specialized hardware.
Have I missed something in my haste
Surely the Z.cash folks are not this myopic.
The following assumption from the Equihash white paper seems to be wrong:
For fixed memory size, memory chips with bandwidth
significantly higher than that of typical desktop memory (such
as DDR3) are rare. Assuming that a prover does not have
access to memory with bandwidth higher than certain
Bw
max
,
we can efficiently bound the time-memory (and thus the time-
area) product for such implementations.
...
To the best of our knowledge, the highest reported band-
width in commercial products does not exceed 200 GB/s
(Playstation 4 has 172 GB/s bandwidth [5]), whereas the
desktop DDR3 can have as high as 17 GB/s bandwidth [3].
Thus we conclude that the highest advantage a prover can
get from parallel hardware does not exceed the factor of 15.
This may mean that our proof-of-work is GPU- and desktop-
friendly, whereas it is also ASIC-resistant in the sense that an
ASIC implementation does not yield smaller time-area product.
I am thinking faster memory bandwidth can be obtained by reading and writing to multiple, redundant independent memory banks simultaneously that are interleaved differently to have disjoint collisions on banks.
Or even if not faster, then perhaps orders-of-magnitude more electrically efficient, since the electric consumption will be primarily in the computation and not in the memory. And computation can be radically optimized on an ASIC.
As I predicted when I wrote in the Monero thread about this the other day, it appears the white paper didn't consider electricity as the most important factor. Duh.