ZTEX USB-FPGA Modules 1.15x and 1.15y: 215 and 860 MH/s FPGA Boards - page 32.

TheSeven

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Quote from: ztex on March 12, 2012, 06:01:47 AM

Quote from: TheSeven on March 10, 2012, 03:44:10 PM

This is kind of a hand written, well optimized firmware for the FPGA, in contrast to the automatically synthesized one that the FPGA boards are currently using. If he continues optimizing it and makes it publicly available, I'd estimate that it will end up in the 300-400MH/s range.

Three single single hash, two stage per sha256 round pipelines does not fit on a LX150. This simply requires more resources than available on the chip.

One stage per sha256 round pipelines as used by eldentyrell are about 30% to 40% slower.

...which I hope will change soon

ztex

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Quote from: TheSeven on March 10, 2012, 03:44:10 PM

This is kind of a hand written, well optimized firmware for the FPGA, in contrast to the automatically synthesized one that the FPGA boards are currently using. If he continues optimizing it and makes it publicly available, I'd estimate that it will end up in the 300-400MH/s range.

Three single single hash, two stage per sha256 round pipelines does not fit on a LX150. This simply requires more resources than available on the chip.

One stage per sha256 round pipelines as used by eldentyrell are about 30% to 40% slower.

testconpastas2

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Quote from: TheSeven on March 11, 2012, 05:14:22 AM

Quote from: testconpastas2 on March 11, 2012, 03:54:27 AM

is it feasible a ztex dual or quad board to adjust prices? Maybe I'm wrong but it seems to me a way to save in pcb costs (and space)

i guess it will be over 800-900€ 150x4€(fpga) + ~200-300€ (pcb) for a 800-900 mhash/s it will be a nice 1€ per Mhash/s

The PCB isn't all that expensive, but there's also things like power regulation on it.
To name dollar prices: The FPGAs cost $160 each, and there don't seem to be bulk discounts as long as you buy less than 1000 of them at once.
So judging from the bulk discounts, the rest of the board, including assembly can't cost more than $50, otherwise he would be selling them at a loss.
This means that there he has at least $165 profit margin per board (for small amounts), more than those FPGAs cost!

Placing more FPGAs on a board doesn't neccessarily make things better because it also increases the risk of board failure.

If you want a cheaper solution, go different board or order real bulk amounts

i thought about 10+ but i thought it will be more easy to manage with less pcbs, sharing power and usb cables.

if you go to 50+ prices becomes 1€ /mhash/s this its ok to me but 50 pcbs will become a little messy. i like this but i would like he made 4 or 2 pfga pcbs for similar price.

REgards

PS: i'm From EU so i'd rather buy this over x6500 and others.

TheSeven

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Quote from: testconpastas2 on March 11, 2012, 03:54:27 AM

is it feasible a ztex dual or quad board to adjust prices? Maybe I'm wrong but it seems to me a way to save in pcb costs (and space)

i guess it will be over 800-900€ 150x4€(fpga) + ~200-300€ (pcb) for a 800-900 mhash/s it will be a nice 1€ per Mhash/s

The PCB isn't all that expensive, but there's also things like power regulation on it.
To name dollar prices: The FPGAs cost $160 each, and there don't seem to be bulk discounts as long as you buy less than 1000 of them at once.
So judging from the bulk discounts, the rest of the board, including assembly can't cost more than $50, otherwise he would be selling them at a loss.
This means that there he has at least $165 profit margin per board (for small amounts), more than those FPGAs cost!

Placing more FPGAs on a board doesn't neccessarily make things better because it also increases the risk of board failure.

If you want a cheaper solution, go different board or order real bulk amounts

testconpastas2

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is it feasible a ztex dual or quad board to adjust prices? Maybe I'm wrong but it seems to me a way to save in pcb costs (and space)

i guess it will be over 800-900€ 150x4€(fpga) + ~200-300€ (pcb) for a 800-900 mhash/s it will be a nice 1€ per Mhash/s

allinvain

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Quote from: SamHa1n on March 10, 2012, 03:25:17 PM

Quote from: allinvain on March 10, 2012, 02:12:32 PM

Quote from: DeepBit on March 07, 2012, 05:00:09 PM

HDD mounting plates ? Nice idea

Indeed! Very elegant idea. I'd like to try it with Icarus boards.

Anyone know where he possibly bought this hdd enclosure? I've been hunting on newegg but can't seem to find something similar. I'm guessing that it was taken from a case though.

Edit: Hmm, I found something similar : http://www.newegg.ca/Product/Product.aspx?Item=N82E16816111045

I still think the one in the picture looks bigger though, but I could be wrong.

Thanks. The rack is by "sans digital". It's two of them stacked.

Cool. Thanks for confirming that. Time to hit up newegg Cheesy

The only thing is that I'm not sure if the icarus boards would work with hd trays ad they aren't following the 3.5" format. X6500 and ztex board would work though.

TheSeven

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Quote from: rupy on March 10, 2012, 03:41:04 PM

Quote from: Turbor on March 10, 2012, 08:40:31 AM

Dr Z. what will be your answer to this ? https://bitcointalksearch.org/topic/algorithmically-placed-fpga-miner-255mhschip-supports-all-known-boards-49971 Any plans on a 3 ring design ?

Hm, can somebody explain how this works like I'm 5 years old?

This is kind of a hand written, well optimized firmware for the FPGA, in contrast to the automatically synthesized one that the FPGA boards are currently using. If he continues optimizing it and makes it publicly available, I'd estimate that it will end up in the 300-400MH/s range.

rupy

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Quote from: Turbor on March 10, 2012, 08:40:31 AM

Dr Z. what will be your answer to this ? https://bitcointalksearch.org/topic/algorithmically-placed-fpga-miner-255mhschip-supports-all-known-boards-49971 Any plans on a 3 ring design ?

Hm, can somebody explain how this works like I'm 5 years old?

SamHa1n

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Quote from: allinvain on March 10, 2012, 02:12:32 PM

Quote from: DeepBit on March 07, 2012, 05:00:09 PM

HDD mounting plates ? Nice idea

Indeed! Very elegant idea. I'd like to try it with Icarus boards.

Anyone know where he possibly bought this hdd enclosure? I've been hunting on newegg but can't seem to find something similar. I'm guessing that it was taken from a case though.

Edit: Hmm, I found something similar : http://www.newegg.ca/Product/Product.aspx?Item=N82E16816111045

I still think the one in the picture looks bigger though, but I could be wrong.

Thanks. The rack is by "sans digital". It's two of them stacked.

allinvain

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Quote from: DeepBit on March 07, 2012, 05:00:09 PM

HDD mounting plates ? Nice idea

Indeed! Very elegant idea. I'd like to try it with Icarus boards.

Anyone know where he possibly bought this hdd enclosure? I've been hunting on newegg but can't seem to find something similar. I'm guessing that it was taken from a case though.

Edit: Hmm, I found something similar : http://www.newegg.ca/Product/Product.aspx?Item=N82E16816111045

I still think the one in the picture looks bigger though, but I could be wrong.

BR0KK

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I got rid of the high speed config issue since i moved my vm to parallels

Turbor

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Dr Z. what will be your answer to this ? https://bitcointalksearch.org/topic/algorithmically-placed-fpga-miner-255mhschip-supports-all-known-boards-49971 Any plans on a 3 ring design ?

DeepBit

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HDD mounting plates ? Nice idea :)

SamHa1n

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ztex

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Quote from: nelisky on March 07, 2012, 04:22:53 AM

So just not sending new work to the board for 5 minutes will trigger low power sounds like a great feature, and if I want to force the FPGA to hold still I can issue a resetFpga() though that means I need to reconfigure it afterwards, correct?

The ultimate low power mode is to reset the FPGA. But this also requires reconfiguration afterwards.

TheSeven

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Quote from: ztex on March 07, 2012, 04:21:00 AM

A few word about interrupt transfers:

Interrupt transfers guarantee a certain latency, e.g. you want to see the mouse pointer moving while you are transferring data to your USB HD.

They do not generate an interrupt on the host computer. They are initiated by the host as any USB transfers, i.e. CPU time for all kind of transfers is about the same. The difference is the latency.

Latency for Bitcoin mining is not an issue:
1. because it doesn't matter if you would receive a share with a delay of 50ms
2. bandwidth is extremely low. Therefore latency is always small if only FPGA boards are connected to the USB.

Yes, you could do the same thing (if you don't mind about latency) with an IN BULK endpoint that NAKs all requests until there is a device-side event. Doing it with an IN INTERRUPT EP additionally guarantees that a request is sent once per frame (for bInterval = 1).
However, IIUC (and I haven't yet looked at nelisky's code in detail), the current interface requires the host software to actively poll for events because the device always responds to the transfer immediately, and not only if there was an event. That way the polling can't be offloaded to the hardware, and thus the effective latency before the miner software notices that there's a share is much higher.

And yes, latency does matter, at least for P2Pool. 100ms more total longpoll + sendshare latency = ~1% more stales.

nelisky

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Quote from: ztex on March 07, 2012, 04:06:12 AM

Quote from: nelisky on March 06, 2012, 05:37:42 AM

Is there a way to stop the FPGA from mining without forcing a reconfigure to get it going again? The use case being many boards loosing network connectivity which will make them go round and round on the same data while waiting for new work, which is wasted electricity.

Already implemented: after about 5 minutes of inactivity the FPGA board enters a low power state. This is implemented in firmware,

But due to the support of backup servers this feature shouldn't be used much.

Backup servers are fine, and they do solve the most common use case but my biggest pain is not pool downtime, rather network issues and no backup pool will help with those.

So just not sending new work to the board for 5 minutes will trigger low power sounds like a great feature, and if I want to force the FPGA to hold still I can issue a resetFpga() though that means I need to reconfigure it afterwards, correct?

ztex

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Quote from: nelisky on March 06, 2012, 09:47:29 AM

Every time you poll ztex board you get 2 x nonce and 2 x goldennonce. The latter is when there's a diff=1 share found and the former is just the last calculated nonce (twice because ztex uses 2 hashers in parallel, I believe).

In order to avoid loss if two shares are found within the poll interval the firmware stores (and returns) the previous solutions too. This is why the output is doubled.

A few word about interrupt transfers:

Interrupt transfers guarantee a certain latency, e.g. you want to see the mouse pointer moving while you are transferring data to your USB HD.

They do not generate an interrupt on the host computer. They are initiated by the host as any USB transfers, i.e. CPU time for all kind of transfers is about the same. The difference is the latency.

Latency for Bitcoin mining is not an issue:
1. because it doesn't matter if you would receive a share with a delay of 50ms
2. bandwidth is extremely low. Therefore latency is always small if only FPGA boards are connected to the USB.

ztex

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Quote from: TheSeven on March 06, 2012, 09:13:51 AM

Isn't the error rate calculated by looking at the shares that the µC uploads to the PC? Or is there some more sophisticated self-testing mechanism on the FPGA?

Error rate is measured by verification of the latest hash value. Error rate measurement based on shares would be inaccurate / slow because in average there would be only one measurement every 20s.

ztex

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Quote from: nelisky on March 06, 2012, 05:37:42 AM

Is there a way to stop the FPGA from mining without forcing a reconfigure to get it going again? The use case being many boards loosing network connectivity which will make them go round and round on the same data while waiting for new work, which is wasted electricity.

Already implemented: after about 5 minutes of inactivity the FPGA board enters a low power state. This is implemented in firmware,

But due to the support of backup servers this feature shouldn't be used much.

Topic: ZTEX USB-FPGA Modules 1.15x and 1.15y: 215 and 860 MH/s FPGA Boards - page 32. (Read 182443 times)