Topic: ZTEX voltmod - page 2. (Read 5074 times)

Thanks

I just love me some ghetto modding!!!  Congrats mate.

This will be my last update or at least for a while, I have achieved maximum clock 248mhz at 1.41V, which is the ztex bitstream limit.
Still waiting for new releases of ET's TML release - maybe we will see some interesting numbers there.

Some changes: redone the soldering with a better equipment, much nicer now,
also added a off/on switch for vmod. Off being default and on starts at 1.3v now due to changed trimmer. Also added HS on some micro hotspots.













Remember kids, ambient temperature is very important, no matter how much air you throw at the chip.

 

Ran 1.355v@236mhash over night - everything is in check. Ambient temp in the room has risen about 10°C in the meanwhile (from 22°C to 32°C), so now an invalid poped up from time to time but ztex didn't lower clock.

I got a hold of some thermal tape and attached a bottom HS. Testing now.

http://shrani.si/f/2D/11A/3b8KJP16/img9220.jpg

http://shrani.si/f/3J/Jg/10zWNYA7/img9222.jpg

http://shrani.si/f/2d/6o/3U6cKOP9/img9224.jpg

Correction, its already working - we are just testing 2 new release candidates as I type.

Also I have x6500 at hand and Icarus, maybe maybe they are ready for some modifications as well, but we need better bitstreams there.

After reading about the difficulties in the tricone mining bitstream I was wondering when someone was going to bump the voltages a bit to solve the instability issues. Perhaps you should chat with eldentyrell and beta test that?

Curious how the MH/w efficiency will be affected with higher voltages and core clocks. FPGA overvolting might make watercooling something to consider. More likely though would be an immersed solution in fluorinert(which can be found for cheap on eBay from time to time).


edit: my mistake, you're one of the guys trying to get eldentyrell's bitstream working on a ztex single.

Nice to see that this is possible.

Now u have to test them on LN2 plz

So it turns up its not really hard to do....

Here are ztex schematics http://www.ztex.de/downloads/usb-fpga-1.15x.pdf

We need to fiddle with R12 and/or R13 to bump the voltage.
Formula to get the voltage is 0.8*(1+R12/R13)

On schema or (high res pic1, high res pic2) we can see:
R13 = 2k4
R12 = 1K3 , pcb print says 1K2 in reality R12 is 1370 ohm, which means (by the formula) default voltage should be 1.256V

VCCINT can be checked here:



and it showed me 1.264V on my multimeter by default.

I decided to go with 50k parallel multi-turn trimmer that would result at 2290ohm instead 2400 at 50k. That should bring us to about 1.28V.

I know its ugly but it works (i redid some of the soldering after seeing this pic). Also it doest matter if the R12 and R13 are shorted because they are anyway via pcb.





The readout on the red and black wire straight after - 1.286V.
This increased my stable hashrate from 216 to 220, ztex miner did try to push higher but it went down to 220.

Time to crank it up, some sources say ztex tested up to 1.4v and for bitfury we know he runs 1.5v in OC mode, Xilinx says it's okay to go up to 1.32v.

Also, I am not responsible for your fried boards.


EDIT:

Results w latest ztex sw/fw, 0% invalid:
1.264V 216mhash //default
1.286V 220mhash
1.300V 228mhash
1.320v 232mhash //Xilinx approved
1.350v 236mhash
1.370v 240mhash
1.390v 244mhash
1.410v 248mhash // tested with extensive cooling,.. this is the max that ztex bitstream can go.