It was the Bitcointalk forum that inspired us to create Bitcointalksearch.org - Bitcointalk is an excellent site that should be the default page for anybody dealing in cryptocurrency, since it is a virtual gold-mine of data. However, our experience and user feedback led us create our site; Bitcointalk's search is slow, and difficult to get the results you need, because you need to log in first to find anything useful - furthermore, there are rate limiters for their search functionality.
The aim of our project is to create a faster website that yields more results and faster without having to create an account and eliminate the need to log in - your personal data, therefore, will never be in jeopardy since we are not asking for any of your data and you don't need to provide them to use our site with all of its capabilities.
We created this website with the sole purpose of users being able to search quickly and efficiently in the field of cryptocurrency so they will have access to the latest and most accurate information and thereby assisting the crypto-community at large.
Content | Score | Started by | Date posted | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]What are the two squares to the left of the FPGAs? Also, an important thing…
|
n/a | Olaf.Mandel | July 15, 2011, 03:37:51 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I wanted to get an idea what the space would look like on this board. This shows…
|
n/a | Olaf.Mandel | July 15, 2011, 02:18:09 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]So long as you stick to only reprogramming these USB AVRs via the factory-p…
|
n/a | Olaf.Mandel | July 14, 2011, 04:15:57 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...][...]My understanding was that it is possible to brick the Atmels. Can you…
|
n/a | Olaf.Mandel | July 14, 2011, 03:50:33 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Nevertheless I would still route the SPI and JTAG interfaces to the DIMM as…
|
n/a | Olaf.Mandel | July 14, 2011, 02:58:47 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]The real question is how much is saved by moving all of this stuff off the…
|
n/a | Olaf.Mandel | July 13, 2011, 02:07:38 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Either I missed something, or it only has a JTAG slave, not a JTAG master. You c…
|
n/a | Olaf.Mandel | July 13, 2011, 02:06:00 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]The dulplex could be used for flashing I/O and sensor (temperature?) commun…
|
n/a | Olaf.Mandel | July 12, 2011, 03:34:21 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Let me try to collect the different suggestions and comments made on bus design…
|
n/a | Olaf.Mandel | July 12, 2011, 04:38:05 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]It's an LX150T, and you may be right that the license won't let me compile…
|
n/a | Olaf.Mandel | July 10, 2011, 04:06:25 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...] I own an LX150 dev kit, and the necessary license to do compiles for it, s…
|
n/a | Olaf.Mandel | July 09, 2011, 03:23:23 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
They may not be specified for 12V, because nobody in the memory industry would e…
|
n/a | Olaf.Mandel | July 06, 2011, 10:16:24 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...] there is a ton of free software to use the FT2232D as a JTAG interface. Th…
|
n/a | Olaf.Mandel | July 06, 2011, 08:47:30 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]I was under the impression that the use of DIMM sockets for power distribut…
|
n/a | Olaf.Mandel | July 06, 2011, 03:30:11 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Is there a sane way to drive 127 SPI slaves through an FTDI?For the FT2232D…
|
n/a | Olaf.Mandel | July 05, 2011, 11:23:51 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]slave-only DIMMs, USB-chip only on backplane: cheapest, JTAG and I2C on bus…
|
n/a | Olaf.Mandel | July 05, 2011, 04:19:55 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Each board will need its dedicated I2C bus anyway, so why not have a dedica…
|
n/a | Olaf.Mandel | July 05, 2011, 03:32:17 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
While the poll for which FPGA to use is running, we can already decide on the sp…
|
n/a | Olaf.Mandel | July 05, 2011, 04:22:44 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Then give the poll your click I scroll down to the end of the discussion t…
|
n/a | Olaf.Mandel | July 05, 2011, 01:59:59 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Xilinx Spartan 6 XC6LX150: cheaper, claims to be faster.
|
n/a | Olaf.Mandel | July 04, 2011, 04:18:51 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]What about the Xilinx XC6SLX150-3CSG484C? It's cheaper than the EP4CE75 and…
|
n/a | Olaf.Mandel | July 04, 2011, 05:23:18 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
New version of the table with lower Altera prices (assuming 1USD=0.6891EUR):Chip…
|
n/a | Olaf.Mandel | July 03, 2011, 04:31:51 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]As far as i see they both require a 2.5 V and a 1.2 V rail.So the only diff…
|
n/a | Olaf.Mandel | July 03, 2011, 04:21:00 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]It seems to be standard to list the number of MHash as the number of total…
|
n/a | Olaf.Mandel | July 03, 2011, 01:58:56 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I just realised something when I read makomk previous post (thanks for the info,…
|
n/a | Olaf.Mandel | July 03, 2011, 09:31:30 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
We still need a decision on which FPGA to use. As there has been no new data, I…
|
n/a | Olaf.Mandel | July 03, 2011, 06:26:14 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I haven't looked at the specs, but don't most chips require the interface pins t…
|
n/a | Olaf.Mandel | June 30, 2011, 03:02:52 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I would expect that can be done via JTAG as well.I meant a USB interface pin con…
|
n/a | Olaf.Mandel | June 30, 2011, 02:58:42 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Is that even needed? Wouldn't it be possible to load an FPGA configuration that…
|
n/a | Olaf.Mandel | June 30, 2011, 01:50:51 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I don't want to kill the project via feature-creep, but if the chips can be indi…
|
n/a | Olaf.Mandel | June 30, 2011, 01:03:42 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
For the standalone board version, perhaps this form-factor is interesting instea…
|
n/a | Olaf.Mandel | June 30, 2011, 12:58:41 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I don't want to kill the project via feature-creep, but if the chips can be indi…
|
n/a | Olaf.Mandel | June 30, 2011, 12:41:04 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]I'm no expert on the hardware design, but there is at least one issue again…
|
n/a | Olaf.Mandel | June 30, 2011, 06:59:13 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Update on Altera speed: This is with using the default settings, in the "Early T…
|
n/a | Olaf.Mandel | June 29, 2011, 06:42:03 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...] Can someone look at the code and tell me if they find the mistake?[...]Don…
|
n/a | Olaf.Mandel | June 29, 2011, 02:45:34 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I tried benchmarking different FPGAs against each other (simulated only, no hard…
|
n/a | Olaf.Mandel | June 28, 2011, 05:58:24 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]The text for the pushbutton sounds like hot-plugging. I don't think we want…
|
n/a | Olaf.Mandel | June 28, 2011, 03:17:55 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
What do you need an Arduino for? The FT2232 does I2C. Edit: Or whatever other US…
|
n/a | Olaf.Mandel | June 28, 2011, 02:25:28 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
What do you need an Arduino for? The FT2232 does I2C. Edit: Or whatever other US…
|
n/a | Olaf.Mandel | June 28, 2011, 01:59:37 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]If we follow my suggestion above a DIMM populated with 1 Altera 80K Cyclone…
|
n/a | Olaf.Mandel | June 28, 2011, 07:56:57 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
How much? and how soon?Price and availability? ... Someone has to draw the thin…
|
n/a | Olaf.Mandel | June 28, 2011, 07:41:52 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Merging the layout of Olaf.Mandel and me this would provide enough space fo…
|
n/a | Olaf.Mandel | June 28, 2011, 06:54:07 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]If we use the 1.2 V voltage regulators proposed by TheSeven we could supply…
|
n/a | Olaf.Mandel | June 28, 2011, 06:17:49 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]How much power will you be pulling through the DIMM bus with this?For the b…
|
n/a | Olaf.Mandel | June 28, 2011, 06:10:31 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I'm thinking of something along the lines of this: http://search.digikey.com/scr…
|
n/a | Olaf.Mandel | June 28, 2011, 05:52:55 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
What about something like this (klick on image to see full size):The board is 45…
|
n/a | Olaf.Mandel | June 28, 2011, 03:57:56 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]This setup is using both front and back of the board for components.This wo…
|
n/a | Olaf.Mandel | June 27, 2011, 06:18:15 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Voltage regulator 18 V to 2.5 V 2.5 W 6x per FPGA http://search.digikey.c…
|
n/a | Olaf.Mandel | June 27, 2011, 06:05:21 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
So one additional interesting question is wich voltages are needed onboard the D…
|
n/a | Olaf.Mandel | June 27, 2011, 01:26:52 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]And I just realised: the backplane needs different I2C interfaces for each…
|
n/a | Olaf.Mandel | June 27, 2011, 10:11:55 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I doubt if this work, 2200 mm2 are 2,2x10 cm, this is a quarter of a normal DIMM…
|
n/a | Olaf.Mandel | June 27, 2011, 08:22:53 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]the 5 V rail of the DIMM socket is used to supply the FPGA peripherals in t…
|
n/a | Olaf.Mandel | June 27, 2011, 08:17:39 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I dont want to rush things but i'd like to ask you to decide please.[...][using…
|
n/a | Olaf.Mandel | June 27, 2011, 08:06:41 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Here is a table that hopefully answers the question if one should use a rail vol…
|
n/a | Olaf.Mandel | June 27, 2011, 07:36:42 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
We are talking about FPGA temperature at the moment. So here a question: do we a…
|
n/a | Olaf.Mandel | June 27, 2011, 06:04:10 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
3 milliohms for the roundtrip? Including inner resistance of the voltage regulat…
|
n/a | Olaf.Mandel | June 27, 2011, 05:53:33 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I would strongly recommend that each board generates all needed currents and vol…
|
n/a | Olaf.Mandel | June 27, 2011, 05:01:19 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
This is my reference for DIMM sockets,http://www.4uconnector.com/online/Itemadra…
|
n/a | Olaf.Mandel | June 27, 2011, 04:50:14 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...][...]If yes, then maybe O_Shovah as the original poster should clarify what…
|
n/a | Olaf.Mandel | June 27, 2011, 04:13:01 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Switching between the jtag-lines of the FTDI and the jtag-lines from the [b…
|
n/a | Olaf.Mandel | June 27, 2011, 01:57:13 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]Having a barrel connector in addition to the molex one definitely can't hur…
|
n/a | Olaf.Mandel | June 26, 2011, 06:20:51 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]The FT2232 operates bus powered (works without having +12V connected).Since…
|
n/a | Olaf.Mandel | June 26, 2011, 06:12:45 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]My suggestion would be the following:- One of those FTDIs on every FPGA/ASI…
|
n/a | Olaf.Mandel | June 26, 2011, 06:08:19 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
How to delete a message? I accidentally created a copy of my previous post and c…
|
n/a | Olaf.Mandel | June 26, 2011, 02:52:20 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]The (mother) board has [...] one Molex 8981 connector for power supply.Only…
|
n/a | Olaf.Mandel | June 26, 2011, 02:50:04 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]- ARM CPU for Mainboard control ( to be determined)[...]For overall system…
|
n/a | Olaf.Mandel | June 26, 2011, 02:35:38 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
We should try to keep the two solution as similar as possible: if the external p…
|
n/a | Olaf.Mandel | June 26, 2011, 02:25:06 PM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]I am more and more thinking about dropping the SPI completely even for the…
|
n/a | Olaf.Mandel | June 26, 2011, 04:44:46 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...] As for JTAG: it can be used, but is it accessible from the design after co…
|
n/a | Olaf.Mandel | June 26, 2011, 04:23:38 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
While i don't think that there would be a shortage of IO-Pins on FPGA i want to…
|
n/a | Olaf.Mandel | June 26, 2011, 04:07:42 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
[...]So let me explain my point of view:One central asumption of my idea is that…
|
n/a | Olaf.Mandel | June 26, 2011, 03:02:26 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
If SPI is adequate for both configuration and data traffic then I'm happy with t…
|
n/a | Olaf.Mandel | June 26, 2011, 03:22:16 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
I2C for FPGA host communications. SPI would require far too many chip select li…
|
n/a | Olaf.Mandel | June 26, 2011, 02:01:08 AM | ||
Modular FPGA Miner Hardware Design Development Development & Technical Discussion
Given the title of this thread this might be a bad question, but here goes: why…
|
n/a | Olaf.Mandel | June 25, 2011, 08:05:29 PM | ||
Newbie restrictions Beginners & Help
How long is the reaction time between the 4h expiring and access being granted?…
|
n/a | Olaf.Mandel | June 25, 2011, 07:58:01 PM | ||
New scalable pipelined FPGA core for SHA-256 - any interest? Beginners & Help
[...]A 64x MUX just needs three 5-bit (32-entry) LUTs for each bit of width [...…
|
n/a | Olaf.Mandel | June 25, 2011, 06:07:22 PM | ||
New scalable pipelined FPGA core for SHA-256 - any interest? Beginners & Help
...I would be happy to post my code on Github, but I feel I really should test &…
|
n/a | Olaf.Mandel | June 25, 2011, 05:26:52 PM | ||
Solo vs. Pooled Mining Network Traffic? Beginners & Help
I would also like to know.But on a different note: do you have that much hardwar…
|
n/a | Olaf.Mandel | June 25, 2011, 04:22:15 PM | ||
Can you run the linux client in console only mode - i.e. no gui? Beginners & Help
[...]Didn't even read the whole part... just the first sentence. It doesn't hur…
|
n/a | Olaf.Mandel | June 25, 2011, 03:58:08 PM | ||
Newbie restrictions Beginners & Help
I saw some complains that people want to participate in non-newbie threads so th…
|
n/a | Olaf.Mandel | June 25, 2011, 03:52:30 PM | ||
Can you run the linux client in console only mode - i.e. no gui? Beginners & Help
That said: I agree that running bitcoind sounds like what you want to do. The qu…
|
n/a | Olaf.Mandel | June 25, 2011, 03:43:34 PM | ||
New scalable pipelined FPGA core for SHA-256 - any interest? Beginners & Help
Hi,short question of unrolling vs. not unrolling the loops: assuming a fully unr…
|
n/a | Olaf.Mandel | June 25, 2011, 03:32:02 PM | ||
Can you run the linux client in console only mode - i.e. no gui? Beginners & Help
Disclaimer: I am new to BitCoins, so I am somewhat shooting from the hip here.Th…
|
n/a | Olaf.Mandel | June 25, 2011, 03:19:56 PM | ||
Introduce yourself :) Beginners & Help
Hi,I am currently interested in FPGA hashing. As long as I stay active, you shou…
|
n/a | Olaf.Mandel | June 25, 2011, 03:11:35 PM |