Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards - page 18.

kakobrekla

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Activity: 714

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Psi laju, karavani prolaze.

Quote from: ?? on ??

Quote from: spiccioli on July 21, 2012, 07:31:58 AM

Quote from: kakobrekla on July 21, 2012, 06:23:22 AM

Quote from: Nachtwind on July 21, 2012, 06:22:04 AM

Is anyone using that bitstream on Ztex Singles? Would like to know if it is somehow usable

H:357/114,114,128 X:272 C:180,180,185 E:0/0,0,0 T:5m

personal best, so far at least.

You have all my envy

spiccioli

I must not understand that block of code.

I was thinking T:5m meant it ran for 5 minutes before failing.

It ran stable, the T is the timeframe for the Error rates (which were 0).
I should add, its a modified ztex single board.

spiccioli

legendary

Activity: 1379

Merit: 1003

nec sine labore

Quote from: kakobrekla on July 21, 2012, 06:23:22 AM

Quote from: Nachtwind on July 21, 2012, 06:22:04 AM

Is anyone using that bitstream on Ztex Singles? Would like to know if it is somehow usable

H:357/114,114,128 X:272 C:180,180,185 E:0/0,0,0 T:5m

personal best, so far at least.

You have all my envy

spiccioli

kakobrekla

hero member

Activity: 714

Merit: 500

Psi laju, karavani prolaze.

Quote from: Nachtwind on July 21, 2012, 06:22:04 AM

Is anyone using that bitstream on Ztex Singles? Would like to know if it is somehow usable

H:357/114,114,128 X:272 C:180,180,185 E:0/0,0,0 T:5m

personal best, so far at least.

Nachtwind

hero member

Activity: 700

Merit: 507

Is anyone using that bitstream on Ztex Singles? Would like to know if it is somehow usable

spiccioli

legendary

Activity: 1379

Merit: 1003

nec sine labore

Quote from: eldentyrell on July 20, 2012, 05:49:24 PM

Quote from: eldentyrell on July 20, 2012, 04:47:14 AM

USERCODE before bitstream upload: 0x657f5ebe

WOW, caught it red-handed: your board is BROKEN. That is supposed to be 0xcafebabe. You are definitely, definitely, definitely getting corruption on your jtag lines.

eldentyrell,

if you look at this message

https://bitcointalksearch.org/topic/m.1042538

and/or at messages 655/656 in this thread you'll see that the value is 0xcafebabe before and after.

Keep in mind that ebereon is not programming his FPGA using urjtag because this does not work, see

https://bitcointalk.org/index.php?topic=49971.msg1022796;topicseen#msg1022796

but using the xc3sprog utility http://xc3sprog.sourceforge.net/ to flash the FPGA and after this running java.

Maybe we should try to use a real jtag cable instead of urjtag through the usb cable.

spiccioli

Keninishna

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Activity: 556

Merit: 500

Quote from: ebereon on July 20, 2012, 05:59:09 PM

Thanks for your reply.

I have 10 boards and i don't think every board is broken, more i think it's something with the array fpga.

Since enterpoint is not cooperating with you in an way we all wish, we can only wait for something to come out to get our boards (~500 in the world) hashing faster then 380MH/s with 4 fpgas...

Thanks anyway.

eb

PS: I have no colors in the cmd unter windows... only the ANSI codes i posted i see in the cmd.

Hey Eb, have you tried this with multiple boards and get the same style of errors? Maybe the enterpoint controller is unstable and we can ask them to address the issue.

Inspector 2211

sr. member

Activity: 448

Merit: 250

"cafe babe" - wow.
Much better than
"dead beef", I think.

ebereon

sr. member

Activity: 397

Merit: 500

Thanks for your reply.

I have 10 boards and i don't think every board is broken, more i think it's something with the array fpga.

Since enterpoint is not cooperating with you in an way we all wish, we can only wait for something to come out to get our boards (~500 in the world) hashing faster then 380MH/s with 4 fpgas...

Thanks anyway.

eb

PS: I have no colors in the cmd unter windows... only the ANSI codes i posted i see in the cmd.

eldentyrell

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Activity: 980

Merit: 1004

felonious vagrancy, personified

Quote from: eldentyrell on July 20, 2012, 04:47:14 AM

Please don't cut-and-paste the ANSI codes. It makes the logs very difficult to read.

Quote from: ebereon on July 20, 2012, 04:57:33 AM

I don't know what you mean, i posted the log i get in the windows cmd, i thought you need the complete log... Will delete these line now.

This:

Quote from: ebereon on July 20, 2012, 04:39:16 AM

←[1m

is an ANSI code. On Linux (every terminal program I've ever seen) and Mac when you copy-and-paste from a terminal window it does not include that stuff. If Windows doesn't work that way and you can't find a terminal program that acts normally, you can use -Dcolor_console=false to simply turn off the color.

Quote from: eldentyrell on July 20, 2012, 04:47:14 AM

USERCODE before bitstream upload: 0x657f5ebe

WOW, caught it red-handed: your board is BROKEN. That is supposed to be 0xcafebabe. You are definitely, definitely, definitely getting corruption on your jtag lines.

Quote from: eldentyrell on July 20, 2012, 04:47:14 AM

java.io.IOException: TML acknowledgement of read operation failed; expected=0x435 got=0x0

Same story here. If a few reads and writes succeed (like "magic number check ok"), and then you get one of these, it is 100% certain that you have signal integrity problems on the JTAG bus.

I am really sorry, but you have data corruption issues on your JTAG bus -- this is a hardware malfunction. You really need to contact your board vendor and work this out with them. The TML definitely isn't going to work properly if the data it sends to the chip is getting corrupted… not a lot I can do about that.

Sorry man, I know this isn't what you want to hear, but this is incontrovertible proof that the bits being sent into the JTAG bus are not the same bits coming out the other end. And, unfortunately, there is nothing that can be done in software or in the bitstream to fix that.

ebereon

sr. member

Activity: 397

Merit: 500

I get different outputs every time i start tml:

Code:

Tricone Mining Logic, host software v1.0

   IF YOU EXPERIENCE HIGH ERROR RATES: try running just one ring at a
   time (e.g. use 'ztex:0:0.0' on command line instead of 'ztex:0').
   If each ring works error free on its own, but you get errors when
   running all three, it means your power supply is sagging.

             adding work source eclipsemc.com
             starting long poll thread
[FT2232         ] ←[35mfound new board urjtag:FT2232←[0m
[urjtag:FT2232:0] ←[35mfound new chip←[0m
[urjtag:FT2232:0] programming FPGA
             USERCODE before bitstream upload: 0xcafebabe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:FT2232:0]   done programming FPGA
[urjtag:FT2232:0] magic number check ok
[urjtag:FT2232:0] ←[35mchip is running bitstream version herbrand, built 5d6h57m
13s ago←[0m
[urjtag:FT2232:0] chip has 3 rings
[urjtag:FT2232:0]   measuring clock frequency at csg484.L22
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
[urjtag:FT2232:0]   measuring clock frequency at fgg484.K20
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
[urjtag:FT2232:0]   measuring clock frequency at fgg484.J1
←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:45s java.io.IOException: TML ackn
owledgement of read operation failed; expected=0x20 got=0xffffffef
        at com.triconemining.board.MiningChip.read(MiningChip.java:68)
        at com.triconemining.miner.ClockRateEstimator.estimateClockRate(ClockRat
eEstimator.java:27)
        at com.triconemining.miner.ChipWrapper.detectClockPin(ChipWrapper.java:3
27)
        at com.triconemining.miner.ChipWrapper.(ChipWrapper.java:70)
        at com.triconemining.miner.BoardWrapper.getChip(BoardWrapper.java:49)
        at com.triconemining.miner.BoardWrapper.run_(BoardWrapper.java:98)
        at com.triconemining.miner.BoardWrapper.run(BoardWrapper.java:73)
        at java.lang.Thread.run(Unknown Source)

eb

ebereon

sr. member

Activity: 397

Merit: 500

after serval time starting tml with your command line i get now this:

Code:

Tricone Mining Logic, host software v1.0

   IF YOU EXPERIENCE HIGH ERROR RATES: try running just one ring at a
   time (e.g. use 'ztex:0:0.0' on command line instead of 'ztex:0').
   If each ring works error free on its own, but you get errors when
   running all three, it means your power supply is sagging.

             adding work source eclipsemc.com
             starting long poll thread
[FT2232         ] ←[35mfound new board urjtag:FT2232←[0m
[urjtag:FT2232:0] ←[35mfound new chip←[0m
[urjtag:FT2232:0] programming FPGA
             USERCODE before bitstream upload: 0xcafebabe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:FT2232:0]   done programming FPGA
[urjtag:FT2232:0] magic number check ok
[urjtag:FT2232:0] ←[35mchip is running bitstream version herbrand, built 5d6h54m
52s ago←[0m
[urjtag:FT2232:0] chip has 3 rings
[urjtag:FT2232:0]   measuring clock frequency at csg484.L22
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:5.2s   |  H:←[1m←[32m0←[0m←[0m E
:←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:5.2s java.io.IOException: TML ac
knowledgement of read operation failed; expected=0x20 got=0xffffffff
        at com.triconemining.board.MiningChip.read(MiningChip.java:68)
        at com.triconemining.miner.ClockRateEstimator.estimateClockRate(ClockRat
eEstimator.java:24)
        at com.triconemining.miner.ChipWrapper.detectClockPin(ChipWrapper.java:3
27)
        at com.triconemining.miner.ChipWrapper.(ChipWrapper.java:70)
        at com.triconemining.miner.BoardWrapper.getChip(BoardWrapper.java:49)
        at com.triconemining.miner.BoardWrapper.run_(BoardWrapper.java:98)
        at com.triconemining.miner.BoardWrapper.run(BoardWrapper.java:73)
        at java.lang.Thread.run(Unknown Source)

ebereon

sr. member

Activity: 397

Merit: 500

Quote from: eldentyrell on July 20, 2012, 04:47:14 AM

Quote from: ebereon on July 20, 2012, 04:39:16 AM

H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:5.2s

Please don't cut-and-paste the ANSI codes. It makes the logs very difficult to read.

I don't know what you mean, i posted the log i get in the windows cmd, i thought you need the complete log... Will delete these line now.

Quote from: eldentyrell on July 20, 2012, 04:47:14 AM

That's interesting. The DCM for ring 0 appears to lock (FT2232:0.0) but ring 1 has problems (FT2232:0.1).

Could you please try this three or four times and check whether you get the exact same result (ring 0 works, ring 1 fails) every time?

Also, please try using the command line

java -jar tml-1.0.jar urjtag:"FT2232":0.0 http://user:[email protected]:8337/

(note the bolded text) to use only ring 0, and see how far that gets.

Ok the second try give me this:

Code:

Tricone Mining Logic, host software v1.0

   IF YOU EXPERIENCE HIGH ERROR RATES: try running just one ring at a
   time (e.g. use 'ztex:0:0.0' on command line instead of 'ztex:0').
   If each ring works error free on its own, but you get errors when
   running all three, it means your power supply is sagging.

             adding work source eclipsemc.com
             starting long poll thread
[FT2232         ] ?[35mfound new board urjtag:FT2232?[0m
[urjtag:FT2232:0] ?[35mfound new chip?[0m
[urjtag:FT2232:0] programming FPGA
             USERCODE before bitstream upload: 0x657f5ebe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:FT2232:0]   done programming FPGA
[urjtag:FT2232:0] magic number check ok
[urjtag:FT2232:0] ?[35mchip is running bitstream version herbrand, built 5d6h37m
53s ago?[0m
[urjtag:FT2232:0] chip has 3 rings
[urjtag:FT2232:0]   measuring clock frequency at csg484.L22
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
[urjtag:FT2232:0]   measuring clock frequency at fgg484.K20
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
[urjtag:FT2232:0]   measuring clock frequency at fgg484.J1
[urjtag:FT2232:0]     measured input clock frequency at 50 Mhz
[urjtag:FT2232:0] assuming input clock frequency of 48 Mhz
[urjtag:FT2232:0] ?[35masserting global reset?[0ms
[urjtag:FT2232:0] ?[31munknown gateware version 0x500234c2?[0m
[urjtag:FT2232:0.0] disabling DCM bypass mux T:50s
[urjtag:FT2232:0.0] opening signcryption channel0s
[urjtag:FT2232:0.0] setting clock to 150 Mhz, mult=25 div=8
H:?[1m?[32m0?[0m?[0m X:0 E:?[1m?[31m0?[0m?[0m T:50s   |  H:?[1m?[32m0?[0m?[0m E:
?[1m?[31m0?[0m?[0m A:?[32m0?[0m R:?[33m0?[0m T:50s java.io.IOException: TML ackn
owledgement of read operation failed; expected=0x435 got=0x0
        at com.triconemining.board.MiningChip.read(MiningChip.java:68)
        at com.triconemining.miner.DCM.progDone(DCM.java:232)
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:145)
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:62)
        at com.triconemining.miner.RingWrapper.setClockFrequency(RingWrapper.jav
a:349)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:256)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:180)
        at com.triconemining.miner.BoardWrapper.run_(BoardWrapper.java:101)
        at com.triconemining.miner.BoardWrapper.run(BoardWrapper.java:73)
        at java.lang.Thread.run(Unknown Source)

The command line you posted give me this:

Code:

Tricone Mining Logic, host software v1.0

   IF YOU EXPERIENCE HIGH ERROR RATES: try running just one ring at a
   time (e.g. use 'ztex:0:0.0' on command line instead of 'ztex:0').
   If each ring works error free on its own, but you get errors when
   running all three, it means your power supply is sagging.

             adding work source eclipsemc.com
             starting long poll thread
[FT2232         ] ←[35mfound new board urjtag:FT2232←[0m
[urjtag:FT2232:0] ←[35mfound new chip←[0m
[urjtag:FT2232:0] programming FPGA
             USERCODE before bitstream upload: 0xcafebabe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:FT2232:0]   done programming FPGA
[urjtag:FT2232:0] magic number check ok
[urjtag:FT2232:0] ←[35mchip is running bitstream version herbrand, built 5d6h43m
43s ago←[0m
[urjtag:FT2232:0] chip has 3 rings
[urjtag:FT2232:0]   measuring clock frequency at csg484.L22
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
[urjtag:FT2232:0]   measuring clock frequency at fgg484.K20
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
[urjtag:FT2232:0]   measuring clock frequency at fgg484.J1
[urjtag:FT2232:0]     measured input clock frequency at 50 Mhz
[urjtag:FT2232:0] assuming input clock frequency of 48 Mhz
[urjtag:FT2232:0] ←[35masserting global reset←[0ms
[urjtag:FT2232:0] ←[31munknown gateware version 0x500234c2←[0m
[urjtag:FT2232:0.0] disabling DCM bypass mux T:50s
[urjtag:FT2232:0.0] opening signcryption channel0s
[urjtag:FT2232:0.0] setting clock to 150 Mhz, mult=25 div=8
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:50s java.io.IOException: DCM PROG
DONE did not go high after programming
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:187)
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:62)
        at com.triconemining.miner.RingWrapper.setClockFrequency(RingWrapper.jav
a:349)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:256)
        at com.triconemining.miner.BoardWrapper.run_(BoardWrapper.java:98)
        at com.triconemining.miner.BoardWrapper.run(BoardWrapper.java:73)
        at java.lang.Thread.run(Unknown Source)

eb

eldentyrell

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Activity: 980

Merit: 1004

felonious vagrancy, personified

Quote from: ebereon on July 20, 2012, 04:39:16 AM

H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:5.2s

Please don't cut-and-paste the ANSI codes. It makes the logs very difficult to read.

Quote

[urjtag:FT2232:0] measuring clock frequency at fgg484.J1
[urjtag:FT2232:0] measured input clock frequency at 50 Mhz

Okay, so far so good.

Quote

[urjtag:FT2232:0.0] setting clock to 150 Mhz, mult=25 div=8
[urjtag:FT2232:0.0] asserting local reset
[urjtag:FT2232:0.1] disabling DCM bypass mux
[urjtag:FT2232:0.1] opening signcryption channel
[urjtag:FT2232:0.1] setting clock to 150 Mhz, mult=25 div=8

That's interesting. The DCM for ring 0 appears to lock (FT2232:0.0) but ring 1 has problems (FT2232:0.1).

Could you please try this three or four times and check whether you get the exact same result (ring 0 works, ring 1 fails) every time?

Also, please try using the command line

java -jar tml-1.0.jar urjtag:"FT2232":0.0 http://user:[email protected]:8337/

(note the bolded text) to use only ring 0, and see how far that gets.

ebereon

sr. member

Activity: 397

Merit: 500

Ok, did programm the herbrand bitstream with enterpoint tools. here is the output with standard flags:

Code:

Tricone Mining Logic, host software v1.0

   IF YOU EXPERIENCE HIGH ERROR RATES: try running just one ring at a
   time (e.g. use 'ztex:0:0.0' on command line instead of 'ztex:0').
   If each ring works error free on its own, but you get errors when
   running all three, it means your power supply is sagging.

             adding work source eclipsemc.com
             starting long poll thread
[FT2232         ] ←[35mfound new board urjtag:FT2232←[0m
[urjtag:FT2232:0] ←[35mfound new chip←[0m
[urjtag:FT2232:0] programming FPGA
             USERCODE before bitstream upload: 0xcafebabe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:FT2232:0]   done programming FPGA
[urjtag:FT2232:0] magic number check ok
[urjtag:FT2232:0] ←[35mchip is running bitstream version herbrand, built 5d6h23m
19s ago←[0m
[urjtag:FT2232:0] chip has 3 rings
[urjtag:FT2232:0]   measuring clock frequency at csg484.L22
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:5.2s   |  H:←[1m←[32m0←[0m←[0m E
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:10s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:15s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:15s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0]   measuring clock frequency at fgg484.K20
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:15s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:20s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:25s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:30s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:35s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0]     measured input clock frequency at 0 Mhz
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:35s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0]   measuring clock frequency at fgg484.J1
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:35s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:40s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:45s   |  H:←[1m←[32m0←[0m←[0m E:
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0]     measured input clock frequency at 50 Mhz
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0] assuming input clock frequency of 48 Mhz
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0] ←[35masserting global reset←[0ms
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0] ←[31munknown gateware version 0x500234c2←[0m
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.0] disabling DCM bypass mux T:50s
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.0] opening signcryption channel0s
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.0] setting clock to 150 Mhz, mult=25 div=8
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.0] ←[35masserting local reset←[0m
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0] ←[31munknown gateware version 0x500234c2←[0m
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.1] disabling DCM bypass mux T:50s
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.1] opening signcryption channel0s
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
[urjtag:FT2232:0.1] setting clock to 150 Mhz, mult=25 div=8
H:←[1m←[32m0←[0m←[0m X:0 E:←[1m←[31m0←[0m←[0m T:50s   |  H:←[1m←[32m0←[0m←[0m E:
←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:50s java.io.IOException: DCM PROG
DONE did not go high after programming
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:187)
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:62)
        at com.triconemining.miner.RingWrapper.setClockFrequency(RingWrapper.jav
a:349)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:256)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:180)
        at com.triconemining.miner.BoardWrapper.run_(BoardWrapper.java:101)
        at com.triconemining.miner.BoardWrapper.run(BoardWrapper.java:73)
        at java.lang.Thread.run(Unknown Source)

Command line: java -jar tml-1.0.jar urjtag:"FT2232" http://user:[email protected]:8337/

eb

eldentyrell

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Quote from: punin on July 20, 2012, 04:35:58 AM

He was running rc5

In the log it says "1.0". The release candidates said "1.0rcX". So he does have the latest software, but he's also using at least a few of the more advanced options. Better to start simple and not override the defaults, at least at first.

New rule for support: you must post the command line and the log, not just the log. Thanks!

punin

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Activity: 560

Merit: 500

Quote from: eldentyrell on July 20, 2012, 04:30:28 AM

Quote from: ebereon on July 20, 2012, 04:22:17 AM

[urjtag:FT2232:0] ←[35mchip is running bitstream version girard, built 6d9h24m43

Could you post the command line you used? It should be selecting bitstream "herbrand" unless you overrode that with other options. Also I don't see the line in there where it tested for a valid input clock (i.e. detected the actual frequency), so it looks like you're clobbering a lot of the defaults.

Please post the command line you used. Really really important. I cannot help you without that.

He was running rc5

eldentyrell

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felonious vagrancy, personified

Quote from: ebereon on July 20, 2012, 04:22:17 AM

[urjtag:FT2232:0] ←[35mchip is running bitstream version girard, built 6d9h24m43

Could you post the command line you used? It should be selecting bitstream "herbrand" unless you overrode that with other options. Also I don't see the line in there where it tested for a valid input clock (i.e. detected the actual frequency), so it looks like you're clobbering a lot of the defaults.

Please post the command line you used. Really really important. I cannot help you without that.

ShadesOfMarble

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Quote from: eldentyrell on July 20, 2012, 04:17:41 AM

You are the only person who has reported this particular problem

ebereon seems to be stuck at the same point.

I don't know a single user who got his CM working with TML, that's why I don't know you how come to your "fully supported" conclusion!? Do you know a single user who got this working? There are a few 100s of people waiting to make full use of their hardware, so please tell use the secret - if there is any Wink

ebereon

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Activity: 397

Merit: 500

My cairnsmore1 test:

Code:

Tricone Mining Logic, host software v1.0

   IF YOU EXPERIENCE HIGH ERROR RATES: try running just one ring at a
   time (e.g. use 'ztex:0:0.0' on command line instead of 'ztex:0').
   If each ring works error free on its own, but you get errors when
   running all three, it means your power supply is sagging.

             adding work source eclipsemc.com
[FT2232         ] ←[35mfound new board urjtag:FT2232←[0m
[urjtag:FT2232:0] ←[35mfound new chip←[0m
[urjtag:FT2232:0] programming FPGA
             starting long poll thread
             USERCODE before bitstream upload: 0xcafebabe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:FT2232:0]   done programming FPGA
[urjtag:FT2232:0] magic number check ok
[urjtag:FT2232:0] ←[35mchip is running bitstream version girard, built 6d9h24m43
s ago←[0m
[urjtag:FT2232:0] chip has 3 rings
[urjtag:FT2232:0] assuming input clock frequency of 48 Mhz
[urjtag:FT2232:0] ←[35masserting global reset←[0m
[urjtag:FT2232:0.0] opening signcryption channel
[urjtag:FT2232:0.0] setting clock to 60 Mhz, mult=5 div=4
java.io.IOException: DCM PROGDONE did not go high after programming
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:187)
        at com.triconemining.miner.DCM.setClockFrequency(DCM.java:62)
        at com.triconemining.miner.RingWrapper.setClockFrequency(RingWrapper.jav
a:349)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:256)
        at com.triconemining.miner.ChipWrapper.enableRing(ChipWrapper.java:180)
        at com.triconemining.miner.BoardWrapper.run_(BoardWrapper.java:98)
        at com.triconemining.miner.BoardWrapper.run(BoardWrapper.java:73)
        at java.lang.Thread.run(Unknown Source)

Any help to get it running eldentyrell? I'm on windows 7 with patched urjtag.

Thanks.
eb

eldentyrell

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Activity: 980

Merit: 1004

felonious vagrancy, personified

Quote from: punin on July 20, 2012, 04:17:50 AM

How about cluster support?

Clusters are fully supported via JTAG.

I am currently running 19 JTAG chains off of a single machine, with up to six (single-chip) boards per chain.

Topic: Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards - page 18. (Read 119444 times)