Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards - page 21.

ebereon

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Here is my patched urjtag -> patched urjtag incl. dll's

You have to install first the official 0.10 urjtag from the webside, then unpack my archive and copy over all files. Please make sure the PATH Variable contains the installation directory of urjtag.

To test it, open a cmd and type jtag
Then type "cable FT2232" in the jtag prompt, now follow the discription on the tml webside to test idcode etc.

If this is working type "q" to quit the jtag programm, then you can start tml-0.999.jar and play with it.

EDIT:
This binary has been compiled to work with cairnsmore1, for other applications I recommend the original binary!

Keninishna

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Quote from: ebereon on July 10, 2012, 08:22:10 PM

ok, got it compiled myself using "BlueJ" Wink

I got some progess on cairnsmore1 without a special jtag cable (just the shipped usb-cable), but not really far...

@Eldentyrell: Please correct the spelling of "cairnsmore" in tml-0.999 it is wrong spelled "carinsmore". Thanks! Wink

If I start it without "preprogramming" I got this:
...

If someone needs a already patched urjtag binary with the needed dll's or the corrected tml-0.999w.jar to play with, I can package it up for download. Eldentyrell, if this is problematic for you I will remove the tml download, but please correct the windows version tml-0.999w.jar, see the error I described in the other post.

I need some sleep now...

eb

LOL this woulda saved me some time. Cross compiling and patching in cygwin is kind of a pain.

ebereon

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Activity: 397

Merit: 500

Quote from: eldentyrell on July 10, 2012, 11:34:28 PM

Quote from: ebereon on July 10, 2012, 08:22:10 PM

If I start it without "preprogramming" I got this:

For the benefit of other users, could you explain exactly what you mean by "preprogramming"?

With "preprogramming" I mean use enterpoint tools to programm the bitstream. tml-0.999 can not programm it, it takes ~10 seconds and I get the error.

punin

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Activity: 560

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I wonder if this could be causing some of the problems the boards are experiencing:

[urjtag:0:0] measuring clock frequency at icarus/carinsmore pin (fgg484.J1)
[urjtag:0:0] measured input clock frequency at 49 Mhz
[urjtag:0:0] assuming input clock frequency of 48 Mhz

eldentyrell

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Quote from: ebereon on July 10, 2012, 08:22:10 PM

If I start it without "preprogramming" I got this:

For the benefit of other users, could you explain exactly what you mean by "preprogramming"?

Quote from: ebereon on July 10, 2012, 08:22:10 PM

USERCODE after bitstream upload: 0xcafebabe [urjtag:0:0] done programming FPGA [urjtag:0:0] magic number check ok

That is very, very good news. It means the bitstream is loaded and communicating properly with the host software. You're almost there!

Quote from: ebereon on July 10, 2012, 08:22:10 PM

java.io.IOException: TML acknowledgement of read operation failed; expected=0x435 got=0xfffffde5

think I got this error because my board is broken. If someone with a healty board can test this, it would be nice - also to see some more success. Cheesy

Yeah, that sounds right. If you get past the "magic number check" but get read-acknowledgement errors later on, it means that there is some flaky hardware somewhere on the communication path. Try slowing down the JTAG clock to something really slow like 500khz.

eldentyrell

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Quote from: ebereon on July 10, 2012, 03:03:02 PM

error translated via google: "no main manifest attribute in tml 0.999w.jar"

Sorry, my mistake. Please re-download (fixed it) and try again.

Keninishna

hero member

Activity: 556

Merit: 500

ebereon

sr. member

Activity: 397

Merit: 500

ok, got it compiled myself using "BlueJ" Wink

I got some progess on cairnsmore1 without a special jtag cable (just the shipped usb-cable), but not really far...

@Eldentyrell: Please correct the spelling of "cairnsmore" in tml-0.999 it is wrong spelled "carinsmore". Thanks! Wink

If I start it without "preprogramming" I got this:

Code:

_________________________________________________________________________
Tricone Mining Logic, host software v0.999

        ** THIS IS A PRE-RELEASE.  NOT FOR PRODUCTION USE **

   Eldentyrell will declare this codebase ready for production use
   once he has converted his own mine to use it (yes, he pays himself
   commissions).  Until then, performance and signcryption server
   uptime are likely to be erratic.

   Here is a partial list of issues you should be aware of:

     - many kinds of errors (network, etc) cause the miner to get stuck
     - only one of the signcryption frontends is contacted
     - clock-rate adjustment is 100% manual, not automatic
     - no overheat protection >>MAKE SURE YOU HAVE A HEATSINK INSTALLED<<


   ******************************************************************
   *                                                                *
   *               IF YOU EXPERIENCE HIGH ERROR RATES:              *
   *                                                                *
   *  Try running just one ring at a time (e.g. use 'ztex:0:0' on   *
   *  command line instead of 'ztex:0').  If each ring works error  *
   *  free on its own, but you get errors when running all three,   *
   *  it means your power supply is sagging.                        *
   *                                                                *
   ******************************************************************

[urjtag:0:0] programming FPGA
             USERCODE before bitstream upload: 0xffffffff
             USERCODE after bitstream upload: 0xffffffff
[urjtag:0:0]   done programming FPGA
Exception in thread "main" java.io.IOException: TML acknowledgement of read operation failed; expected=0x1 got=0xffffffff
        at com.triconemining.board.MiningChip.read(MiningChip.java:65)
        at com.triconemining.bitcoin.miner.Miner.checkMagicNumber(Miner.java:210)
        at com.triconemining.bitcoin.miner.Miner.(Miner.java:34)
        at com.triconemining.bitcoin.miner.Main$1.(Main.java:414)
        at com.triconemining.bitcoin.miner.Main.main(Main.java:414)

Ok, I now programmed the "davis" bistream with enterpoint tools, and now I got this:

Code:

_________________________________________________________________________
Tricone Mining Logic, host software v0.999

        ** THIS IS A PRE-RELEASE.  NOT FOR PRODUCTION USE **

   Eldentyrell will declare this codebase ready for production use
   once he has converted his own mine to use it (yes, he pays himself
   commissions).  Until then, performance and signcryption server
   uptime are likely to be erratic.

   Here is a partial list of issues you should be aware of:

     - many kinds of errors (network, etc) cause the miner to get stuck
     - only one of the signcryption frontends is contacted
     - clock-rate adjustment is 100% manual, not automatic
     - no overheat protection >>MAKE SURE YOU HAVE A HEATSINK INSTALLED<<


   ******************************************************************
   *                                                                *
   *               IF YOU EXPERIENCE HIGH ERROR RATES:              *
   *                                                                *
   *  Try running just one ring at a time (e.g. use 'ztex:0:0' on   *
   *  command line instead of 'ztex:0').  If each ring works error  *
   *  free on its own, but you get errors when running all three,   *
   *  it means your power supply is sagging.                        *
   *                                                                *
   ******************************************************************

[urjtag:0:0] programming FPGA
             USERCODE before bitstream upload: 0xcafebabe
             USERCODE after bitstream upload: 0xcafebabe
[urjtag:0:0]   done programming FPGA
[urjtag:0:0] magic number check ok
[urjtag:0:0] chip is running bitstream version davis, built 6 days, 19 hours ago
[urjtag:0:0] design is intended for input clock frequency of 48 Mhz
[urjtag:0:0] measuring clock frequency at ztex pin (csg484.L22)
[urjtag:0:0] measured input clock frequency at 0 Mhz
[urjtag:0:0] measuring clock frequency at nexus6/x6500 pin (fgg484.K20)
[urjtag:0:0] measured input clock frequency at 0 Mhz
[urjtag:0:0] measuring clock frequency at icarus/carinsmore pin (fgg484.J1)
[urjtag:0:0] measured input clock frequency at 49 Mhz
[urjtag:0:0] assuming input clock frequency of 48 Mhz
[urjtag:0:0] chip has 3 rings
[urjtag:0:0:0] opening signcryption channel
[urjtag:0:0:0] setting clock to 157 Mhz, mult=23 div=7   |  H:←[1m←[32m0←[0m←[0m E:←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:1.0s
[urjtag:0:0:0]     ramping clock: mult=8 div=7   T:15m   |  H:←[1m←[32m0←[0m←[0m E:←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:1.0s
[urjtag:0:0:0]     ramping clock: mult=9 div=7   T:15m   |  H:←[1m←[32m0←[0m←[0m E:←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:1.0s
H:←[1m←[32m0←[0m←[0m X:0 C: E:←[1m←[31m0←[0m←[0m T:15m   |  H:←[1m←[32m0←[0m←[0m E:←[1m←[31m0←[0m←[0m A:←[32m0←[0m R:←[33m0←[0m T:1.0s Exceptio
H:←[1m←[32m0←[0m←[0m/←[32m0←[0m X:0 C:0 E:←[1m←[31m0←[0m←[0m/←[31m0←[0m T:15m   |  H:←[1m←[32m0←[0m←[0m/←[32m0←[0m E:←[1m←[31m0←[0m←[0m/←[31m0←
[0m A:←[32m0←[0m R:←[33m0←[0m T:40s java.io.IOException: TML acknowledgement of read operation failed; expected=0x435 got=0xfffffde5
        at com.triconemining.board.MiningChip.read(MiningChip.java:65)
        at com.triconemining.bitcoin.miner.DCM.progDone(DCM.java:199)
        at com.triconemining.bitcoin.miner.DCM.setClockFrequency(DCM.java:169)
        at com.triconemining.bitcoin.miner.DCM.setClockFrequency(DCM.java:86)
        at com.triconemining.bitcoin.miner.Ring.setClockFrequency(Ring.java:278)
        at com.triconemining.bitcoin.miner.Miner.enableRing(Miner.java:190)
        at com.triconemining.bitcoin.miner.Miner.enableRing(Miner.java:121)
        at com.triconemining.bitcoin.miner.Main.main(Main.java:426)
Exception in thread "Thread-2" java.lang.RuntimeException: java.io.EOFException
        at com.triconemining.limp.LimpConnection.run(LimpConnection.java:53)
        at java.lang.Thread.run(Unknown Source)
Caused by: java.io.EOFException
        at com.triconemining.util.VarInt.read(VarInt.java:16)
        at com.triconemining.limp.LimpConnection.run(LimpConnection.java:50)
        ... 1 more

I think I got this error because my board is broken. If someone with a healty board can test this, it would be nice - also to see some more success. Cheesy

tml-0.999 is using FPGA3 if we take enterpoints numbering, so it's enough to "preprogramm" only FPGA3 to play with tml-0.999.
I used the dip switch settings for twin_test but SW6#1 on to get 48 Mhz!

I will continue with tests when my new boards arrive Wink

If someone needs a already patched urjtag binary with the needed dll's or the corrected tml-0.999w.jar to play with, I can package it up for download. Eldentyrell, if this is problematic for you I will remove the tml download, but please correct the windows version tml-0.999w.jar, see the error I described in the other post.

I need some sleep now...

eb

ebereon

sr. member

Activity: 397

Merit: 500

hmm, this is not working for me:

Code:

D:\=TML=>java -jar tml-0.999w.jar urjtag:FT2232 http://user:[email protected]:9332/
kein Hauptmanifestattribut, in tml-0.999w.jar

error translated via google: "no main manifest attribute in tml 0.999w.jar"

ebereon

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Activity: 397

Merit: 500

Quote from: eldentyrell on July 10, 2012, 02:51:48 PM

Quote from: ebereon on July 10, 2012, 02:40:40 PM

Ok, i'm not a java programmer, but if you could give me a hint how to recompile it, i will do Wink

See above; I've posted a fixed jar file (0.999w).

nice move! thanks, will test it now Cheesy

eldentyrell

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Quote from: ebereon on July 10, 2012, 02:40:40 PM

Ok, i'm not a java programmer, but if you could give me a hint how to recompile it, i will do Wink

See above; I've posted a fixed jar file (0.999w).

ebereon

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Activity: 397

Merit: 500

Quote from: eldentyrell on July 10, 2012, 02:38:38 PM

Ah, let me guess, you're using Windows? It's a line-ending bug in the TML software. I will fix this in 1.0. In the meantime if you can use a Mac or Linux machine that should work. Otherwise, unpack tml.jar and insert this on line 77 of com/triconemining/jtag/Urjtag.java and recompile:

Code:

        if (i == '\r') i = br.read();

Yep, i use windows

Ok, i'm not a java programmer, but if you could give me a hint how to recompile it, i will do Wink

Thanks.

eb

eldentyrell

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Quote from: ebereon on July 10, 2012, 02:33:15 PM

thanks for your reply.

But you see the urjtag output i posted?

Code:

...
jtag> help tdo
Usage: tdo
jtag> tdo
0
jtag>

Ah, let me guess, you're using Windows? It's a line-ending bug in the TML software. I will fix this in 1.0. In the meantime ~~if you can use a Mac or Linux machine that should work. Otherwise, unpack tml.jar and insert this on line 77 of com/triconemining/jtag/Urjtag.java and recompile:~~

Code:

        if (i == '\r') i = br.read();

[/s]

Edit: I've posted an updated tml-0.999w.jar with this fix.

eldentyrell

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Quote from: chrisp on July 10, 2012, 11:39:06 AM

I've had similar problems attempting to run it with the built-in 4232. Could possibly be related to the undocumented DIP switch functions. If enterpoint would only publish a schematic, or even a .ucf for their board, we could happily have native support in no time.

Dumb stuff like this is why I am not writing any more proprietary-board-interface drivers myself.

Quote from: chrisp on July 10, 2012, 11:39:06 AM

Yohan: Please release a pinout or ucf file for your board, I will happily write the java interface.

That's great! Please stop by irc.tricone-mining.com if you have any questions about how the Java interface works. It is really unbelievably simple; you just have to tell it how to wiggle the three output wires and read the one input wire. There's an optional fifth API call for high-speed "bulk uploads" but it's not required (though it does make the board start up a whole lot faster.

ebereon

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Activity: 397

Merit: 500

Quote from: eldentyrell on July 10, 2012, 02:30:26 PM

Hi Eberon, the answer is right there in the output!

Quote from: ebereon on July 10, 2012, 08:50:28 AM

i have tried the last TML version on cairnsmore1 with the following result with the buildin usb to jtag FTDI chip FT4232:

Code:

'xception in thread "main" java.io.IOException: garbled output from urjtag; did you rememeber to apply the patch?  got character '

You did not apply this patch to urjtag. That's why it didn't work.

If you know the urjtag developers, please encourage them to upstream the patch. In the meantime you must apply it first.

thanks for your reply.

But you see the urjtag output i posted?

Code:

...
jtag> help tdo
Usage: tdo
jtag> tdo
0
jtag>

eldentyrell

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Hi Eberon, the answer is right there in the output!

Quote from: ebereon on July 10, 2012, 08:50:28 AM

i have tried the last TML version on cairnsmore1 with the following result with the buildin usb to jtag FTDI chip FT4232:

Code:

'xception in thread "main" java.io.IOException: garbled output from urjtag; did you rememeber to apply the patch?  got character '

You did not apply this patch to urjtag. That's why it didn't work.

If you know the urjtag developers, please encourage them to upstream the patch. In the meantime you must apply it first.

ebereon

sr. member

Activity: 397

Merit: 500

eldentyrell, i don't know if you read the other thread, so i post this here for you:

Quote from: yohan on July 10, 2012, 12:57:23 PM

Quote from: chrisp on July 10, 2012, 11:40:28 AM

Quote from: yohan on July 10, 2012, 08:26:24 AM

Quote from: ShadesOfMarble on July 10, 2012, 07:13:14 AM

Quote from: yohan on July 10, 2012, 06:37:39 AM

As far as I understand it you can use a programming cable to run ET bitstream already and there is even a chance our front end might just work anyway. Urjtag has support for a FT2232 a very close relative of the FT4232 we use on Cairnsmore1.

Which cable do I need? Your prog3 cable? Is it supported by urjtag?

We have not proven either hardware with urjtag. Our Prog3 is a Xilinx cable clone and in theory would work urjtag as Xilinx cable is on the support list. That said there are a range of Xilinx cables and it is possible our clone is one not supported. We know Prog3 works fully with Xilinx tools and that has always been our benchmark.

The in-built FT4232 on Cairnsmore1 is a big brother version of the FT2232 that is on the urjtag support list. It has the same JTAG processing features so that is why it might work.

I've had significant problems attempting to run it with the built-in 4232. Could possibly be related to the (undocumented) DIP switch functions / settings. If enterpoint would only publish a schematic, or even a .ucf for their board, we could happily have native support in no time.

Yohan: Please release a pinout or ucf file for your board, I will happily write the java interface.

Chris

This is probably what you need to know and it is quite simple.

JTAG_TCK         <= USBC_0 WHEN SWITCH8 = '0' ELSE 'Z';
JTAG_TDI         <= USBC_1 WHEN SWITCH8 = '0' ELSE 'Z';
USBC_2         <= JTAG_TDO;
JTAG_TMS         <= USBC_3 WHEN SWITCH8 = '0' ELSE 'Z';

USBC_0 is bus that runs directly from the FT4232 to the controller and USBC_0 is PortA bit0, USBC_1 is PortA bit 1, USBC_2 is PortA bit2 and USBC_3 is PortA bit3. So basically the JTAG runs off the lower 4 bits Port A on the FT4232. The only direct effect is switch8 which is the top bit of the switches at the controller. It's used as an isolator if we want to plug in a separate cable. So if you write as if it's directly connected to the FT4232 you won't go far wrong. Default setting should have this interface connected.

It is worth switching switch3 to off during programming as that stops all the clocks and makes programming more reliable.

We will add dip switch setting eventually to the user manual which needs a final pass through for release. We are still doing some changes to these on different builds to what they do exactly but for most people if they are left in the normal published defaults they won't have a problem. Once we move out of the development phase all of this will stabilise and should be much simplier. We will also remove many of the dip switch uses and they simply won't have any effect in later controller builds.

could that help to integrate cairnsmore1 native support to your TML Bitstream?

eb

norulezapply

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Activity: 481

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Quote from: chrisp on July 10, 2012, 11:39:06 AM

Quote from: ebereon on July 10, 2012, 08:50:28 AM

hi eldentyrell,

i have tried the last TML version on cairnsmore1 with the following result with the buildin usb to jtag FTDI chip FT4232:

Do you know what's wrong here? jtag connect to the cable and "idcode" shows 4x XC6SLX150 FPGAs. It also look's like successfully patched with the "tdo" command.

Can you help here?

Thank you!

eb

I've had similar problems attempting to run it with the built-in 4232. Could possibly be related to the undocumented DIP switch functions. If enterpoint would only publish a schematic, or even a .ucf for their board, we could happily have native support in no time.

Yohan: Please release a pinout or ucf file for your board, I will happily write the java interface.

Chris

Best off reposting this in the Cairnsmore1 thread - https://bitcointalk.org/index.php?topic=78239.1240;topicseen
And PM'ing yohan directly. EDIT: whoops! looks like you did already

I'm sure a lot of people would appreciate this!

chrisp

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Quote from: ebereon on July 10, 2012, 08:50:28 AM

hi eldentyrell,

i have tried the last TML version on cairnsmore1 with the following result with the buildin usb to jtag FTDI chip FT4232:

Do you know what's wrong here? jtag connect to the cable and "idcode" shows 4x XC6SLX150 FPGAs. It also look's like successfully patched with the "tdo" command.

Can you help here?

Thank you!

eb

I've had similar problems attempting to run it with the built-in 4232. Could possibly be related to the undocumented DIP switch functions. If enterpoint would only publish a schematic, or even a .ucf for their board, we could happily have native support in no time.

Yohan: Please release a pinout or ucf file for your board, I will happily write the java interface.

Chris

ebereon

sr. member

Activity: 397

Merit: 500

no special cable just the usb cable to the cairnsmore. It support jtag via the FTDI Chip.

Topic: Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards - page 21. (Read 119444 times)