Done.
intron
intron
Looking forward to seeing this USB solution in the general public's hands
Keep up the great work.
Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 31. (Read 176728 times)
August 07, 2013, 06:43:16 PM
Looking forward to seeing this USB solution in the general public's hands
Keep up the great work.
August 07, 2013, 06:39:56 PM
Done.
intron
intron
Looking forward to seeing this USB solution in the general public's hands
Keep up the great work.
August 07, 2013, 04:26:47 PM
Thanks for reply.
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:
top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane
Am i correct?
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:
top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane
Am i correct?
A small board with a single bitfury can be a bi-layer indeed.
Wouldn't take changes when making a board with many ASICs
Here you can see the different layers:
Layer top is Vcore (0V6..0V9), rest is GND with vertical
going wires on layer 3 and horizontal going wires
going on layer 2. Except near the upper edge
were current density is low. Layer bottom is also GND.
In the power section layer top is also GND.
intron
Thanks intron for sharing the board layers.
It is not very clear how do you connect the grounds together.
As i understand the chips 49 pin (GND) is connected to the blue (lowest ground). Also the capacitors near the chips goes to the lowest ground. Am i correct?
There are also a lot of vertical vias. Do they connect the yellow and green grounds?
The ground tab of the ASIC has an 5x5 array of vias
connecting all layers together. Same holds for the
decoupling caps: one terminal is connected to the
top layer (Vcore), the other terminal is connected to
layer 1, 2 and bottom using a via. You don't see the
copper pours in the image for clearity.
These strips of vias connecting all ground planes
together are there to make sure the return path of
the currents are un-interrupted. And as vias are
(almost) free, I do a lot. Just in case:)
intron
August 07, 2013, 03:36:00 PM
Thanks for reply.
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:
top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane
Am i correct?
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:
top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane
Am i correct?
A small board with a single bitfury can be a bi-layer indeed.
Wouldn't take changes when making a board with many ASICs
Here you can see the different layers:
Layer top is Vcore (0V6..0V9), rest is GND with vertical
going wires on layer 3 and horizontal going wires
going on layer 2. Except near the upper edge
were current density is low. Layer bottom is also GND.
In the power section layer top is also GND.
intron
Thanks intron for sharing the board layers.
It is not very clear how do you connect the grounds together.
As i understand the chips 49 pin (GND) is connected to the blue (lowest ground). Also the capacitors near the chips goes to the lowest ground. Am i correct?
There are also a lot of vertical vias. Do they connect the yellow and green grounds?
August 07, 2013, 03:07:47 AM
Done.
[SWEET LOOKING HEAT SINK IMAGE HERE]
intron
[SWEET LOOKING HEAT SINK IMAGE HERE]
intron
That is a piece art deco industrial elegance which I would display proudly.
Lovely work.
August 07, 2013, 02:08:01 AM
Done.
intron
Looks sexy. Not overkill for the small device?intron
No idea, we must see what happens with the first
prototype. Did measurements on a USB Block Erupter
though and they got rather hot:
intron
August 07, 2013, 01:57:51 AM
Done.
intron
Looks sexy. Not overkill for the small device?intron
August 07, 2013, 01:51:50 AM
Done.
intron
intron
August 07, 2013, 01:35:04 AM
And here we go...
Got a bit excited about doing those holes?
August 07, 2013, 01:32:13 AM
And here we go...
August 07, 2013, 01:14:10 AM
n1 intron!
August 07, 2013, 01:02:43 AM
Heatsink is nearly finished, only the screw holes are missing yet.
(Must wait for the guys to show up though,
was the first to arrive in the workshop.
Can't wait:)
intron
(Must wait for the guys to show up though,
was the first to arrive in the workshop.
Can't wait:)
intron
August 06, 2013, 10:04:57 PM
would this heatsink also be placed on the backside of the chip?
Yes, the bottom layer is kept clear fromcomponents, so the heatsink will fit
snugly. Just like the USB Block Erupters.
Not sure if it will be fixed with bolts or heat
conducting glue.
intron
Bolts would be best, it allows hardcore users to swap for thier own heatsink designs more easily and with no damage to the unit (unlike removing glued components)
Yes, but they require drill holes in the PCB,
taking space and breaking up the copper
pours. Hope this gives no problems.
The first board will have three holes for
M2 screws. Rather not use smaller sizes
then M3, but there is not much room.
intron
August 06, 2013, 10:02:05 PM
What hash rate are you expecting from it?
4..5 GH/s to start with.
intron
August 06, 2013, 09:31:26 PM
would this heatsink also be placed on the backside of the chip?
Yes, the bottom layer is kept clear fromcomponents, so the heatsink will fit
snugly. Just like the USB Block Erupters.
Not sure if it will be fixed with bolts or heat
conducting glue.
intron
Bolts would be best, it allows hardcore users to swap for thier own heatsink designs more easily and with no damage to the unit (unlike removing glued components)
CAn I still get in on the TEsting?
... I used to do computer testing for Digital pre-press enterprise systems as well as building games and websites. I have running 20 Blocker Erupters for a few months now and am comfortable hacking with hardware. I can create good bug reports. - digeros August 06, 2013, 09:01:14 PM
would this heatsink also be placed on the backside of the chip?
Yes, the bottom layer is kept clear fromcomponents, so the heatsink will fit
snugly. Just like the USB Block Erupters.
Not sure if it will be fixed with bolts or heat
conducting glue.
intron
Bolts would be best, it allows hardcore users to swap for thier own heatsink designs more easily and with no damage to the unit (unlike removing glued components)
August 06, 2013, 08:19:30 PM
Working on bi•fury now, a dual bitfury USB device.
It will have two bitfury ASICs, user settable
overclocking options and a temperature sensor
to provide for overtemperature protection.
Very early stage though, no idea yet if we will
get it hashing:)
intron
What hash rate are you expecting from it?It will have two bitfury ASICs, user settable
overclocking options and a temperature sensor
to provide for overtemperature protection.
Very early stage though, no idea yet if we will
get it hashing:)
intron
August 05, 2013, 07:43:55 AM
Hey intron,
would this heatsink also be placed on the backside of the chip?
regards
would this heatsink also be placed on the backside of the chip?
regards
Yes, the bottom layer is kept clear from
components, so the heatsink will fit
snugly. Just like the USB Block Erupters.
Not sure if it will be fixed with bolts or heat
conducting glue.
intron
August 05, 2013, 07:39:20 AM
Hey intron,
would this heatsink also be placed on the backside of the chip?
regards
would this heatsink also be placed on the backside of the chip?
regards
August 05, 2013, 07:28:35 AM
Might need a heatsink also:
intron
intron
Jump to: