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Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 27. (Read 176728 times)

-ck
legendary
Activity: 4088
Merit: 1631
Ruu \o/

I'm very happy to see support for the BeagleBone!


Full disclosure:  the current cgminer is very RPi specific.  Some code hacking is necessary before BB will work!
That's an understatement  Roll Eyes Oh and it's not "the current cgminer", it's the forked code based on an older version. I received a bitfury USB stick from 101BTC and I've spent a lot of time trying to get it working on a PC instead of an RPi and it's proving far from trivial... Some of the memory and hardware hacks just don't even exist outside of the RPi and some I haven't remotely figured out what they do.
full member
Activity: 125
Merit: 100
Working on bin-fury, a bitfury binner:

It has a clamp shell socket that can hold an ASIC
and using firmware a sequence of test patterns
and voltages is applied while measuring the response.
A OLED display is used for displaying the results.

For all your 'champ or tramp' tests:)

intron

I would avoid the tall chinese sockets.  I think I ruined a chip on one.  High ESR due to the size of the loop between the power pins and ground bolt.  The service record on the power supply said it was calibrated in early May.  You can find, albeit expensive, low profile ceramic test sockets that are for low ESR.  The wiring is reminiscent of wire bonding.
KNK
hero member
Activity: 692
Merit: 502
Full disclosure:  the current cgminer is very RPi specific.  Some code hacking is necessary before BB will work!
I have just posted a thread about this problem - https://bitcointalksearch.org/topic/unified-miners-communication-protocol-282034
Pretty soon it will became a nightmare to find the correct software for your hardware, so i would like to invite all software and hardware developers to comment on what they need as communication between the two
ssi
member
Activity: 70
Merit: 10

I'm very happy to see support for the BeagleBone!


Full disclosure:  the current cgminer is very RPi specific.  Some code hacking is necessary before BB will work!
hero member
Activity: 630
Merit: 500
https://pbs.twimg.com/media/BSUpPk0CIAA2YGU.jpg


I lack a level shifter.  Should be here tomorrow.

what you lack in level shifters, you make up for in density - nice work!

how do foresee mounting it?

Honestly I didn't give a lot of thought to mounting when trying to get these prototypes spun quickly Smiley  Next rev will have more options.  For this one, I can just 3d print something with slots.

However, what I DID think about:

it supports RPi:



AND Beaglebone:



I'm very happy to see support for the BeagleBone!
hero member
Activity: 631
Merit: 500
Four more chips ordered, I hope they come quick!


Meanwhile, have these four hashing away on my desk at work:

https://pbs.twimg.com/media/BSmoBr-CAAA5lXq.jpg

Smiley

cool. that seems quite useful.
ssi
member
Activity: 70
Merit: 10
Working on bin-fury, a bitfury binner:

It has a clamp shell socket that can hold an ASIC
and using firmware a sequence of test patterns
and voltages is applied while measuring the response.
A OLED display is used for displaying the results.

For all your 'champ or tramp' tests:)

intron

Sweet!  I was just thinking about something similar yesterday. 
sr. member
Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
Working on bin-fury, a bitfury binner:



It has a clamp shell socket that can hold an ASIC
and using firmware a sequence of test patterns
and voltages is applied while measuring the response.
A OLED display is used for displaying the results.

For all your 'champ or tramp' tests:)

intron
ssi
member
Activity: 70
Merit: 10
Four more chips ordered, I hope they come quick!


Meanwhile, have these four hashing away on my desk at work:



Smiley
ssi
member
Activity: 70
Merit: 10
and changing the clock doesn't seem to change the average hashrate much.  My clock is currently at ... 0xFF 0x10
If using cgminer please note reverse clock bits order, so you have to set 0xff 0x01, 0xff 0x03, ... , 0xff 0x3f, 0xff 0x7f, otherwise your clock will be 8-bits aligned.

Beautiful... getting somewhere now!


 (5s):10.79G (avg):8.436Gh/s | A:205  R:6  HW:0  WU:117.9/m


that's at:


Code:
unsigned char osc6[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x00 };


Bottom side of the board is at 29C.
Great Job!



Thanks Dave Smiley

It's time for more chips; putting in an order now.
vip
Activity: 472
Merit: 250
and changing the clock doesn't seem to change the average hashrate much.  My clock is currently at ... 0xFF 0x10
If using cgminer please note reverse clock bits order, so you have to set 0xff 0x01, 0xff 0x03, ... , 0xff 0x3f, 0xff 0x7f, otherwise your clock will be 8-bits aligned.

Beautiful... getting somewhere now!


 (5s):10.79G (avg):8.436Gh/s | A:205  R:6  HW:0  WU:117.9/m


that's at:


Code:
unsigned char osc6[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x00 };


Bottom side of the board is at 29C.
Great Job!
full member
Activity: 140
Merit: 100
It's not necessary, but you could use this to verify the SPI chain is working correctly.

makes sense - thanks for clarifying.

I'm not using external clock, and no I didn't feed the final SPI outs back anywhere.

ah - this is line used to program chips internal oscillator (libbitfury.c line#109):

Code:
unsigned char osc6[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x00 };

I'd assumed the Pi was generating external clock for the chips using the above code.
The separate clock connection on the H-board threw me off - guessing c-scape added that to keep the functionality available.

EDIT: reworded for posterity
ssi
member
Activity: 70
Merit: 10
wow - guess i need to switch to using external clock  Smiley

Do you have the last chip in your chain feeding SPI outs back into the Pi as on the M / H boards?
I've yet to figure out why this is done.

I'm not using external clock, and no I didn't feed the final SPI outs back anywhere.
sr. member
Activity: 251
Merit: 250
Do you have the last chip in your chain feeding SPI outs back into the Pi as on the M / H boards?
I've yet to figure out why this is done.
It's not necessary, but you could use this to verify the SPI chain is working correctly.
full member
Activity: 140
Merit: 100
wow - guess i need to switch to using external clock  Smiley

Do you have the last chip in your chain feeding SPI outs back into the Pi as on the M / H boards?
I've yet to figure out why this is done.
ssi
member
Activity: 70
Merit: 10
Beautiful... getting somewhere now!


 (5s):10.79G (avg):8.436Gh/s | A:205  R:6  HW:0  WU:117.9/m


that's at:


Code:
unsigned char osc6[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x00 };

nice - what's your SPI clock set to?  legkodymov's code defaults to 200KHz

5MHz
full member
Activity: 140
Merit: 100
Beautiful... getting somewhere now!


 (5s):10.79G (avg):8.436Gh/s | A:205  R:6  HW:0  WU:117.9/m


that's at:


Code:
unsigned char osc6[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x00 };

nice - what's your SPI clock set to?  legkodymov's code defaults to 200KHz
ssi
member
Activity: 70
Merit: 10
ssi
member
Activity: 70
Merit: 10
and changing the clock doesn't seem to change the average hashrate much.  My clock is currently at ... 0xFF 0x10
If using cgminer please note reverse clock bits order, so you have to set 0xff 0x01, 0xff 0x03, ... , 0xff 0x3f, 0xff 0x7f, otherwise your clock will be 8-bits aligned.

Beautiful... getting somewhere now!


 (5s):10.79G (avg):8.436Gh/s | A:205  R:6  HW:0  WU:117.9/m


that's at:


Code:
unsigned char osc6[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x00 };


Bottom side of the board is at 29C.
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