Well, we all know how good Spondoolies' projections turn out to be. With AM, Bitfury and Spondoolies all talking 0.2 J/Gh for the next generation of ASICs early next year, 0.05 J/Gh mid 2015 for the generation after that is clearly marketing bullshit.
With total absence of a reliable technical information about the chips it is hard to make predictions. About the only source available are the "preliminary data sheets". But even with those one could make educated guesses.
1) If the future chips still contain BIST circuitry/instructions that means that they still weren't able to internalize their own experience that dedicated test circuitry is nearly a complete waste of silicon resources and that the chips have to be continuously calibrated while running, not just tested at the start.
Other things that may indicate that they were finally capable of doing a true full custom/analog design:
2) BIST is still present, but no longer gives binary result PASS/FAIL, but some vector of values
3) PLL programming information will have additional parameters besides "frequency", either duty cycle (instead of the default 50%) or explicit phase shifts (for multi-phase clocking)
4) package information showing more than one "core" voltage, eg. positive Vdd and negative Vss (in addition to ground GND)
(3) and (4) would mean that they are capable of exploiting imperfections in the "C" of "CMOS".
Edit: Anyway, there is a Jewish proverb (approximately): Don't ask the tailor if the suit he's making is going to fit you.