Thanks Bonam for the "2nd Draft" button.
- How far behind Intel's 14nm tech is ASICMINER for SHA-256 (as opposed to CPU-type tech) relative to companies like KnCMiner's 20nm chips (in terms of the research curve)?
AM chips are currently 40 nm. That can be considered "3 generations" behind 14 nm processes. The process size of gen 4 has not been disclosed as far as I know.
- How do the processes required (regardless of the cost) for wafering scale when wafering CPU chips vs. SHA or other encryption-based ASICs? For example, if Intel is able to use ion lithography and AM is unable to gain access to this manufacturing technology for SHA ASIC manufacturing, what are the limiting factors that prevent them from doing so?
The main factors are scale and cost. To use the very latest manufacturing technologies, investments in the hundreds of millions - billions are required. AM can clearly not make these investments. No semiconductor production plant will take the time to set up a billion dollar cutting edge machine that can be cranking out premium chips for Intel for a side job for a few hundred k.
- What is the fabrication process, how does it compare between processor/circuit types?
Research is heavily focused on EUV lithography (using 13.5nm light), while current advances in manufacturing have mainly been relying on multi-patterning. There is also research in electron beam lightography. You'd likely have to talk to an industry expert for details on how/if different lithographic techniques are applied to different types of integrated circuits. I would guess that the primary determinant of the technique used is the desired feature size.
- Why do SHA-256 chip producers alone have so much variance between the node lengths of their chips (i.e. why is AM only at the 28/45nm stage?), and what factors still allow them to be profitable (e.g. cheap manufacturing, cheap design, bulk ordering, resale margins/transfer costs) at the chip market level?
Bitcoin mining ASIC manufacturers started with very limited capital and had to use very cheap lithographic techniques, that is, ones many generations old, hence use of 65nm - 100nm+ processes in 1st generation offerings from various companies. As companies have made profits from first generations, those have been re-invested into more advanced and more expensive chips. However, the process size is not the only determinant of chip efficiency, as there are many ways to optimize a chip on a hardware level in terms of power consumption, computation performance, heat dissipation, etc. None of the ASIC manufacturers have reached anywhere close to the theoretical limits of performance of an SHA256 ASIC at a given process size, and so it is possible to be competitive with larger process sizes by having a better optimized chip. Additionally, production cost and other expenses that determine the sale price of chips have a major impact on competitiveness.
- What does the general technology roadmap look like for ASIC manufacturers in the SHA-256 market? As a point of reference, how might this compare to the Scrypt market, and what technological factors or challenges (i.e. those other than the market value of related coins) are specific to circuit design between these algorithms vs. CPUs?
Bitcoin mining ASIC development has benefited from being able to quickly skip through the generations of processes in a very short time. Those easy performance gains are about to come to an end as many manufacturers are hitting the 20 nm range, near the technological cutting edge. From there on out, they'll have to wait for technology to advance to benefit from any further size reductions and will have to focus on design optimization and cost control.