Topic: [Применение чипов Bitfury], схемные решения и т.п. - page 32. (Read 141720 times)

1	AIfDSo	54	2.019	1.987	141	1	0	1	188	[0:0]	627	9 9 9 8 8 9 9 9 9 9 8 9 9 9 9 9 	0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 
2	AIfDSo	54	2.233	2.093	156	3	0	0	198	[0:1]	622	10 10 10 10 10 10 9 10 9 10 10 10 10 9 10 9 	0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 
3	AIfDSo	54	2.090	2.093	146	4	0	0	198	[0:2]	627	9 10 10 10 9 9 9 9 9 9 8 9 9 9 9 9 	0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 
4	AIfDSo	54	1.661	2.230	116	2	0	0	211	[0:3]	656	8 8 8 7 7 7 7 6 6 7 7 7 7 8 8 8 	0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 
5	AIfDSo	54	2.090	2.188	146	6	0	0	207	[0:4]	621	9 9 8 10 10 10 9 9 9 9 9 9 8 9 9 10 	1 1 2 0 0 0 1 0 0 0 0 0 1 0 0 0 
6	AIfDSo	54	2.291	2.230	160	2	0	0	211	[0:5]	614	10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 	0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 
7	AIfDSo	54	2.305	2.241	161	1	0	0	212	[0:6]	613	10 10 10 9 10 10 11 11 10 10 10 10 10 10 10 10 	0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 
8	AIfDSo	54	2.319	2.220	162	2	0	0	210	[0:7]	617	10 10 10 10 11 10 11 11 10 10 10 9 10 10 10 10 	0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 
9	AIfDSo	54	2.176	2.040	152	2	0	0	193	[0:8]	622	9 10 10 10 10 10 9 10 10 10 10 8 9 9 9 9 	0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 
10	AIfDSo	54	1.976	2.040	138	2	0	0	193	[0:9]	624	9 9 9 9 9 9 8 8 8 7 9 9 9 9 9 8 	0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
11	AIfDSo	54	2.448	2.547	171	5	0	0	241	[0:A]	602	11 11 10 9 11 10 11 11 11 11 11 11 11 10 11 11 	0 0 1 2 0 1 0 0 0 0 0 0 0 1 0 0 
12	AIfDSo	54	2.677	2.494	187	2	0	0	236	[0:B]	600	12 12 12 12 12 12 12 12 12 12 11 12 11 10 11 12 	0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 
13	AIfDSo	54	2.749	2.505	192	6	0	0	237	[0:C]	592	12 11 12 11 12 12 12 11 12 12 12 13 12 13 13 12 	0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 0 
14	AIfDSo	54	2.233	2.611	156	11	0	0	247	[0:D]	621	9 9 10 10 10 10 9 8 9 10 11 10 11 11 9 10 	1 1 0 0 0 0 1 2 1 1 0 1 0 0 2 1 
15	AIfDSo	54	2.634	2.505	184	4	0	0	237	[0:E]	599	11 12 12 12 11 11 11 10 11 12 12 12 11 12 12 12 	1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 
16	AIfDSo	54	2.620	2.558	183	3	0	0	242	[0:F]	600	11 11 12 12 12 12 11 12 12 12 12 12 11 11 9 11 	0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 
17	AIfDSo	54	2.763	2.590	193	5	0	0	245	[1:0]	588	12 13 12 13 13 13 13 12 12 12 12 12 11 11 11 11 	0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 
18	AIfDSo	54	2.448	2.558	171	8	0	0	242	[1:1]	602	11 10 11 11 11 10 11 11 10 12 12 10 10 9 11 11 	0 1 0 0 0 1 0 0 1 0 0 1 1 2 0 1 
19	AIfDSo	54	2.892	2.452	202	6	0	0	232	[1:2]	580	13 13 13 13 11 13 13 13 12 12 13 13 12 12 13 13 	0 0 0 0 2 0 0 0 1 1 0 0 1 1 0 0 
20	AIfDSo	54	2.133	2.494	149	12	1	0	236	[1:3]	619	10 9 9 9 8 11 10 10 8 8 9 9 9 10 10 10 	0 1 1 1 2 0 0 0 2 2 1 1 1 0 0 0 
21	AIfDSo	54	3.035	2.653	212	8	0	0	251	[1:4]	578	13 12 13 14 12 13 14 14 14 14 14 13 14 13 13 12 	0 1 0 0 2 1 0 1 0 0 0 1 0 1 0 1 
22	AIfDSo	54	2.219	2.410	155	6	0	0	228	[1:5]	619	10 10 10 10 10 10 10 10 10 9 10 10 8 8 10 10 	0 0 0 0 0 0 0 0 0 1 0 1 2 2 0 0 
23	AIfDSo	54	2.176	2.494	152	7	0	0	236	[1:6]	622	10 10 10 10 9 10 8 10 10 9 10 9 8 10 10 9 	0 0 0 0 1 0 2 0 0 1 0 0 2 0 0 1 
24	AIfDSo	54	2.734	2.621	191	4	0	0	248	[1:7]	589	12 12 12 12 12 11 11 12 12 11 12 12 12 12 13 13 	1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 
25	AIfDSo	54	2.176	2.642	152	12	0	0	250	[1:8]	624	8 9 9 9 9 10 11 11 9 9 9 10 10 10 10 9 	2 1 1 1 1 0 0 0 2 2 1 0 0 0 0 1 
26	AIfDSo	54	2.649	2.516	185	10	0	0	238	[1:9]	593	12 11 10 11 11 11 12 11 12 12 12 12 12 12 12 12 	0 1 2 1 2 2 1 1 0 0 0 0 0 0 0 0 
27	AIfDSo	54	3.150	2.579	220	9	0	0	244	[1:A]	562	14 14 13 14 12 13 14 13 15 14 15 15 14 13 13 14 	0 0 1 0 2 1 0 2 0 1 0 0 0 1 1 0 
28	AIfDSo	54	2.935	2.568	205	7	0	0	243	[1:B]	585	13 14 13 13 13 13 13 12 12 13 13 13 13 12 13 12 	1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 2 
29	AIfDSo	54	2.391	2.621	167	26	0	0	248	[1:C]	610	11 11 12 10 12 11 9 10 10 8 11 9 9 12 10 12 	1 1 0 2 1 1 3 2 2 4 1 3 3 0 2 0 
30	AIfDSo	54	3.164	2.632	221	10	0	0	249	[1:D]	566	13 14 14 14 14 14 15 15 15 15 13 12 13 13 13 14 	1 0 0 1 1 1 0 0 0 0 1 2 1 1 1 0 
31	AIfDSo	54	2.792	2.558	195	9	0	0	242	[1:E]	588	13 12 13 11 11 12 13 13 12 13 13 11 12 12 11 13 	0 1 0 2 2 1 0 0 1 0 0 1 0 0 1 0 
32	AIfDSo	54	2.434	2.357	170	5	0	0	223	[1:F]	608	11 11 11 11 11 11 11 11 11 10 10 10 10 10 11 10 	0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 
33	AIfDSo	54	2.520	2.579	176	7	0	0	244	[2:0]	598	10 11 11 11 11 11 10 9 11 12 12 12 12 10 12 11 	1 0 0 0 0 0 1 2 1 0 0 0 0 2 0 0 
34	AIfDSo	54	2.863	2.653	200	19	0	0	251	[2:1]	591	12 13 10 12 13 11 13 13 10 13 14 13 14 12 13 14 	2 0 3 1 0 2 1 1 4 1 0 1 0 2 1 0 
35	AIfDSo	54	2.777	2.642	194	8	0	0	250	[2:2]	596	13 12 12 12 12 11 12 13 12 12 12 11 12 12 13 13 	0 0 0 0 0 1 0 0 1 1 1 2 1 1 0 0 
36	AIfDSo	54	2.692	2.611	188	5	0	0	247	[2:3]	592	11 11 12 12 12 11 12 12 12 12 12 12 12 13 12 10 	1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 2 
37	AIfDSo	54	2.706	2.558	189	15	0	0	242	[2:4]	599	11 12 12 10 11 13 12 12 13 10 12 13 13 11 13 11 	2 0 0 2 1 0 1 1 0 3 1 0 0 2 0 2 
38	AIfDSo	54	2.004	2.357	140	3	0	0	223	[2:5]	632	8 9 9 9 9 9 8 9 9 9 8 9 8 9 9 9 	1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 
39	AIfDSo	54	1.761	2.103	123	22	0	0	199	[2:6]	646	9 8 9 7 7 8 7 8 8 7 7 6 7 9 7 9 	0 1 0 2 2 1 2 1 2 2 2 3 2 0 2 0 
40	AIfDSo	54	2.692	2.558	188	7	0	0	242	[2:7]	595	11 12 12 11 12 11 12 12 10 11 11 12 13 13 13 12 	1 0 0 1 0 1 0 0 2 1 1 0 0 0 0 0 
speed:2160 noncerate[GH/s]:98.627 (2.466/chip) hashrate[GH/s]:97.389 good:6889 errors:286 spi-errors:1 miso-errors:1 jobs:334 (record[GH/s]:0.000)
0:	864	36.522	36.582	2551	56	0	1
1:	864	42.091	40.746	2940	144	1	0
2:	432	20.015	20.061	1398	86	0	0 

	config_reg(1,0); 
        config_reg(2,0);

 Configuration registers 7,8,9,10,11 - enable scan chain. All should be UNPROGRAMMED. Or instead of calculating useful jobs chip will activate scanchain
   of selected columns 
 Configuration register 6 - if UNPROGRAMMED - output to OUTCLK is taken straight from INCLK pin, if PROGRAMMED - output to OUTCLK is
   taken from internal clock bus 

 Clock stages - first we take INCLK as input 
 1st stage: Configuration register 4 - if UNPROGRAMMED - then INCLK is fed to next oscillator stage if PROGRAMMED then programmable-delay slow oscillator
   output is MUXED to clock next clock stage 
 2nd stage: Configuration register 1 - if UNPROGRAMMED - then feedthrough clock to next stage, if PROGRAMMED then value of configuration register 0 is
   taken as clock signal (useful for single-step evaluation mode) 
 Configuration register 2 - if UNPROGRAMMED then feedthough clock, if PROGRAMMED then fast ring oscillator is active and feeds next stage 
 Configuration register 3 - if UNPROGRAMMED then clock is divided by 2, if PROGRAMMED then clock is fed directly to internal clock bus 
 Config register 5 - reserved for future use 

 Addresses and their use:

0000 0001 Xlll ebbb - PROGRAM START/STOP SIGNALS
 lll 0 - PC MAX, 1 - ELNS, 2 - WLNS, 3 - RRSTN, 4 - WRSTN, 5 - WLN, 6 - ELN, 7 - WNON
 e - 1 - STOP, 0 - START bbb - bits 0..6 (7 bits) to match against PROGRAM COUNTER.

AEW (without address translation) load:
0001 rj0w wwwb bbbb - Where wwww is round expander position (0..15), bbbbb is bit number, j - is job number and q is 0 for first round, 1 for second round
0001 rj10 0eeb bbbb - Loading AL register
0001 rj10 1aab bbbb - Loading EL register

ATR (address-translated load):
0011 xxaa ooob bbbb address        - CONVERTING ADDRESS TO LOAD EXACTLY NEXT JOB FOR NEXT SCANNING:
 - midstate3 vector
 - midstate0 vector
        - W vector
Done by uploading of 19 32-bit values (single uploaded job)
On read-back first 16 32-bit words read back - found nonces, last 3 32-bit words is current job - 0 or 1. Programming is done to job that currently
is not SCANNED for valid solutions. All others read-back addresses return just current scan-chain output. Server (or controller) side should track
new nonces that were found by a chip and program it quickly enough to keep number of answers within adequate limits, otherwise answers will be lost.

0101 xxxx xxaa aaaa - INTERNAL OSCILLATOR PROGRAMMING (THERMOMETER CODE)
0110 xxxx xxaa aaaa - SLOW INTERNAL OSCILLATOR PROGRAMMING (THERMOMETER CODE)
x111 xxxa aaab bbbb - CONFIGURATION REGISTER MAGIC NUMBER PROGRAMMING.

Slow versus fast oscillators. Slow oscillator should give more uniform delay and less jitter for lower frequencies, while fast oscillator
could give higher frequencies, but less stability at lower frequencies (could means that it behaves instable in SPICE, how it will in reality
though is not known, while slow is definitely works under all conditions).

	spi_clear_buf(); /* Обнуление счетчика буфера*/
	spi_emit_break(); /* Сброс, заставляет чип слушать*/
	spi_emit_fasync(chip_n); /* Выбор чипа*/
	spi_emit_data(0x6000, (void*)osc6, 8); /* Задает частоту внутреннего генератора */
	config_reg(7,0); config_reg(8,0); config_reg(9,0); config_reg(10,0); config_reg(11,0);  /* Настройки для отладки чипа */
	config_reg(6,1); /* Включает вывод клока на 5 пине */
	config_reg(4,1); /* 1=Включает внутренний генератор, 0=Включает внешний генератор, сигнал подавать через 12 пин */
	config_reg(1,0); 
        config_reg(2,0); 
        config_reg(3,0); /* 0=Включает делитель частоты на 2, 1=Отключает делитель частоты*/

0x0F = b00001111
0x1F = b00011111
0x3F = b00111111
0x7F = b01111111
0xFF = b11111111

int spi_txrx(const char *wrbuf, char *rdbuf, int bufsz)
{
	int fd;
	int mode, bits, speed, rv, i, j;
	struct timespec tv;
	struct spi_ioc_transfer tr[16];

	memset(&tr,0,sizeof(tr));
	mode = 0; bits = 8; speed = 200000;

// Thermometer code from left to right - more ones ==> faster clock!