And the part that is a pain though, is his opensource code doesn't include any project files, settings, or configurations, and it requires a fairly elaborate setup mixing multiple tools for various subsections of the bitstream in order to get it to build at all without failing hard. None of this is documented or provided (without extraordinary measures in digging up the info)
You should be able to build ngzhang's Icarus miner using just ISE's built-in synthesis tools, it's actually a relatively straightforward combination of bits from various existing miner projects that were originally meant to be built that way. The options to achieve this are a bit esoteric though - it's the nature of the beast really. I just did a SmartXplorer run on a dual-core and it hit Fmax = 166 MHz in under 24 hours; not quite what I was aiming for but not too shabby.
I agree that you *should* because it's derived from ztex, and if you found a way to do it in pure ISE using some of ztex's notes that's awesome.
The main problem is that the icarus code as-is fails par because it can't fit it into the chip. I've tried several optimization options and it just downright fails. And based on posts from ngzhang himself, I was able to confirm he in fact uses a bit of a strange method, he synthesizes the sha256 core itself seperately in a seperate ise project, using some specific optimization flags, then he passes the ngd into the fpgaminer_top project, and synthesizes that using synplify pro, and THEN does an implementation phase based on the synthesized top level, and the already built sha256 core.
So I've reversed my build out of this. Plus my build now includes some custom logic, and a bunch of custom constraints, and completely different clocking code. Plus some other modifications.
But ultimately yes, closing timing is just a function of a massive smartxplorer run. I can hit lower clock rates fairly easily on a couple passes. But optimizing for 200Mhz is a problem. (my last smartxplorer run ran for nearly a week, and was unable to close 200Mhz, but it came damn close).
Anyway, if you want to try to pull this off on your own, then more power to you, My primary day to day job isn't FPGA development, so I'm probably not as skilled as someone who is a professional at this day in and day out
. I'm always up for a little competition. Or if you want to collaborate, we can likely negotiate terms to share the bounty if you want to contribute to my existing effort.
Either way I'll keep pushing on this, and I hope to have the bitstream running very soon.