Topic: Cairnsmore1 - Quad XC6SLX150 Board - page 16. (Read 286370 times)

Woohoo! Dynamic Clocking!

This bitstream is now mining stable on all 4 slots on both the old (pre-50) and newer CM1 boards.

For me this bitstream is stable, and doesn't suffer from the unfortunate longterm stability problems of the last release. (it's been tested for the past 24h stable on my dev boards)

I no longer need to include multiple speeds. As the dynamic clocking allows this chip to run at any speed the software chooses. It will automatically hone in on an optimal clock speed.

NOTE ON DYNAMIC CLOCKING:
The bitstream only adds a new command to the enhanced protocol. It allows the mining software (mpbm, cgminer, whatever) to send a command to set the clock multiplier to X. This allows stepping up/down the clock speed in 2.5Mhz incriments. I have put hard limits of 50Mhz - 220Mhz in the bitstream (which could be unlocked with fpga editor, I'm not telling you how though lol). For safety. That said, MPBM's feature allows you to set a soft cap on the clock speed. Which it will not clock above. I reccomend setting this limit to 200Mhz for longterm use. As Enterpoint has expressed concerns about pushing the clock higher. On my tests it worked fine up to 220Mhz, but it did increase the external temperature. Enterpoint has been sent a sample of this bitstream for validation, I would reccomend waiting on their response before pushing the chips higher.

Also, be aware, dynamic clocking will take about 30Min - 1Hour to reach the initial peak speed. Then it could take up to 24h total to fully stabilize all your stats. (using MPBMs features, since it's in the software, others may do it differently).

I've also measured the thermals on this one, on my dev board with an IR thermometer, sampled across wide area, over 10 seconds, taking peak reading. After the board is running for 24h on the bitstream (while under solid mining load).

On the previous 175oc Release which has been the stable one up until now:
Ambient Room Temperature 23.5C
Heatsinks 32.1C
Bottom of board 46.5C

On the current release with limits set to 220Mhz to do thermal testing, after 24h of runtime:
Ambient Room Temperature 25.1C
Heatsinks 34.8C
Bottom of board 49.1C

This controller is the same as the previous releases. If you aren't already running a HashVoodoo controller, you must install it. Otherwise you can leave the controller alone.

The controller generates a 25Mhz comm clock, and a 25Mhz LVDS source clock, which is then stepped up. We'll be cleaning that up in a future release, which may improve stability a little more due to less noise.

The LEDs on the array FPGAs work as follows:
RED: Heartbeat (clock blinker) blinks on a divider of the hashing clock, also lights solid in the event of DCM failure
GREEN: Found Nonce (lights up and fades out)
BLUE: Serial Activity LED (lights on RX or TX, then fades out)
AMBER: Idle, lights when the FPGA is not currently busy hashing.
The heartbeat will also light SOLID if the DCM has lost it's lock or the clock is somehow "invalid"

Note: This will work with any Icarus compatible Miner. BUT it will not allow the dynamic clocking feature to work unless the miner supports the new HashVoodoo enhanced protocol. Without dynamic clocking this bitstream will end up locked at it's "safe" clock speed of 150Mhz.

Currently the only "confirmed" supported miner is MPBM. Using the latest version of the "testing" branch from:
https://github.com/TheSeven/Modular-Python-Bitcoin-Miner
Using the cairnsmore worker module.

For those who want to tinker, I've included the appropriate build files (NCD and PCF files) allowing you to use the Xilinx FPGA Editor utility to poke around at the bitstream. Please only do this if you know what you're doing. If you fry your board I can not be held responsible!

For Flashing:
I have included both the normal bit and the MCS file (for flashing the SPI in Impact) in this release.
Only the bit is included for the controller, as an MCS is not needed for it.

NOTE: When programming via either method, you should follow the following suggestions closely, these have been tried on a number of "troublesome" boards, and have helped in every case, so this is now the "official" reccomended method of flashing the SPI:
- Always disconnect power AND USB from the board, THEN set dip switches for programming
- Once dip switches set, re-apply power
- Wait until the FPGAs have all settled before plugging in JTAG or USB
- When programming, first WIPE all 4 SPI chips, starting with chip 0, working up to chip 3
- After all chips are wiped, you can begin programming
- Program the chips one at a time, in reverse order (starting with chip 3, working back to chip 0)
- When done do a full power cycle, allowing chips to settle again before connecting USB
 
To flash via USB use the instructions provided by enterpoint. Attached is a JPG with the dip switch diagram, and here is a table of what the dip switches do:
SWITCH1 - Manual Reset when OFF (default is ON)
SWITCH2 - Override Fan Speed Sense when OFF (default is ON)
SWITCH3 - USB Programming Enable when OFF (default is ON)
SWITCH4 - MUST BE ON ALWAYS!
SWITCH5 - MUST BE ON ALWAYS!
SWITCH6 - Controller USB SPI Flash Enable when OFF (default is ON)
SWITCH7 - NOT USED CURRENTLY
SWITCH8 - JTAG Select (ON=Internal USB) (OFF=External JTAG)

For mining all switches should be in the ON state.

To flash via Xilinx ISE Impact with a supported JTAG cable:
Flash the controller first:
- Plug into controller jtag
- Let impact create a new file, and scan the jtag. 
- It will identify the Spartan3, and prompt if you wish to pick a configuration file
- Choose the controller bit file.
- In the actions menu choose the option to program FLASH and FPGA.

Then do the array FPGAs:
- Plug into array jtag
- Let impact create a new file and scan the jtag
- when prompted, choose the hashvoodoo bit file for configuration file
- When prompted to add an SPI flash, say yes
- Choose the MCS file provided
- When prompted for the type of SPI PROM choose the M25P128
- Repeat for the other 3 chips
- When done a dialog with some settings will pop up, accept the defaults.
- Select one of the SPI Flash chips in the graphical display. It will turn green
- In the action menu choose Program.
- Repeat for the other chips. (no need to do the FPGAs themselves they program from the SPI on power cycle)
- Power cycle the board

When done programming, please do a FULL power cycle of the board before mining with it.

Please share your results with this bitstream on the forums.

Upcoming features:
- HashVoodoo Core (when the REAL performance should start happening!)