Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED - page 43.

Truthchanter

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Activity: 689

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Quote from: Eliovp on March 23, 2017, 10:30:44 AM

Quote from: Truthchanter on March 23, 2017, 10:24:34 AM

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

If you have one of the first 4G samsung batches, it will work and even improve even more. (because you can unlock those to 8G)
If you have a newer batch of those 4G samsung's, it will most probably run but won't run stable.

Greetings

Interesting thanks! I have the old ones and actually used one of your old public bios on em Cheesy

Eliovp

legendary

Activity: 1050

Merit: 1293

Huh?

Quote from: Truthchanter on March 23, 2017, 10:24:34 AM

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

If you have one of the first 4G samsung batches, it will work and even improve even more. (because you can unlock those to 8G)
If you have a newer batch of those 4G samsung's, it will most probably run but won't run stable.

Greetings

Truthchanter

sr. member

Activity: 689

Merit: 253

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

nerdralph

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Activity: 588

Merit: 251

Quote from: lpedretti on March 22, 2017, 10:58:32 PM

Quote from: nerdralph on March 22, 2017, 01:57:50 PM

Quote from: laik2 on March 22, 2017, 09:38:14 AM

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 3, CL = 22, TM = 0, WR = 23, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

I think you are off by +1 with the MR0 CAS latency. SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?

The CAS latency in MR0 is just four bits (A3-A6), so it is based on a table lookup. H5GQ1H24AFR supported all possible latencies from 5 to 20. Micron's EDW4032BABG brief says "Programmable CAS latency: 6–27", so some latencies in the range cannot be programmed. I don't have a Samsung datasheet for the K4G4 series (or any Samsung for that matter), so I would have to reverse-engineer the values from the straps by comparing the MR0 values to CL from SEQ_CAS_TIMING.

Eliovp

legendary

Activity: 1050

Merit: 1293

Huh?

Quote from: laik2 on March 23, 2017, 06:25:35 AM

Quote from: sp_ on March 23, 2017, 06:02:55 AM

What is the most you can squeeze out of a r9 390 ?

A LOT

watercooled 390 can hash ~37/8

Definitely! You can crank those babies up (390 Nitro's) to as good as 40Mh. (Huge OC though..)

laik2

sr. member

Activity: 652

Merit: 266

Quote from: sp_ on March 23, 2017, 06:02:55 AM

What is the most you can squeeze out of a r9 390 ?

A LOT

watercooled 390 can hash ~37/8

Wolf0

member

Activity: 81

Merit: 1002

It was only the wind.

Sometimes loosening the timings is better, and clocking higher - specifically on Eth.

KL0nLutiy

member

Activity: 158

Merit: 10

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

is it suit for sapphire rx 480 (Samsung)?

sp_

legendary

Activity: 2926

Merit: 1087

Team Black developer

What is the most you can squeeze out of a r9 390 ?

MikeBuzz

member

Activity: 68

Merit: 10

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Using that strap i am getting 29.5mhs @ 1180/2050

laik2

sr. member

Activity: 652

Merit: 266

Quote from: lpedretti on March 22, 2017, 10:58:32 PM

Quote from: nerdralph on March 22, 2017, 01:57:50 PM

Quote from: laik2 on March 22, 2017, 09:38:14 AM

Quote from: nerdralph on March 22, 2017, 09:10:26 AM

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes). Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 3, CL = 22, TM = 0, WR = 23, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

I think you are off by +1 with the MR0 CAS latency. SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?

You are missing MR8

EDIT: tRCDW/A and tRP_WRA are lower for other reason. Try yours on Cryptonight and then mine - u'll see the diff.
Hint: ARB_DRAM_TIMING.ACTRD/ACTWR can go lower

deadsix

hero member

Activity: 751

Merit: 517

Fail to plan, and you plan to fail.

Quote from: Eliovp on March 22, 2017, 04:37:24 PM

Seems like the samsung one doesn't have global offset.

Stock roms with global offset have either '03' +18.75mV value or '04' +25mV as VDDC offset.
I've never seen something else, or rather negative offset.. and i've opened up a lot of them ;-) 'But correct me if i'm wrong..'

Greetings.

Thank you Good sir.

lpedretti

full member

Activity: 152

Merit: 100

Quote from: nerdralph on March 22, 2017, 01:57:50 PM

Quote from: laik2 on March 22, 2017, 09:38:14 AM

Quote from: nerdralph on March 22, 2017, 09:10:26 AM

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes). Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 3, CL = 22, TM = 0, WR = 23, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

I think you are off by +1 with the MR0 CAS latency. SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?

Wolf0

member

Activity: 81

Merit: 1002

It was only the wind.

Quote from: nerdralph on March 21, 2017, 03:01:21 PM

I've been looking at more of the strap data that most people ignore, and I'm thinking there could be some important data there. Based on some information in a PM, after MC_SEQ_MISC_TIMING2 comes MC_SEQ_MISC1, which supposedly contains mode register 1/0, and the next 32 bits is mode register 5/4. GDDR5 specifies 10 Mode Registers to define the specific mode of operation. Some of the mode register data appears to be duplicated elsewhere in the strap, while some is not. For example MC_SEQ_MISC_TIMING2 has CRC read/write latency, and that is part of MR4 (2 bits for read latency and 3 bits for write latency).

I seem to recall both Wolf and Eliovp mentioning there is some important timing in the mode registers.

There are - we'll be publishing more soon.

nerdralph

sr. member

Activity: 588

Merit: 251

Quote from: nerdralph on March 22, 2017, 06:19:48 PM

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

You've got tRCDW(A) at 14 instead of 16, which shouldn't make any difference at all with ETH since it's all DAG reads. The tighter R2W and RP_WRA shouldn't make a difference for the same reason. Looser timing for RP_RDA (12 vs 11) might help stability, but I'm not having any stability problems. After 3 hrs of ETH mining at 28.3Mh, sgminer is showing just 45 HW errors.

update:
I tried tRC = 62 instead of 73, and got no speed increase (and then crash). I tried RCDR(A)=22 instead of 24, and got no increase in speed but a big increase in errors. So then I tried yours and I get a slight increase (~28.4 vs 28.3).

update2:
It looks like the performance increase comes from ARB_DRAM_TIMING.ACTRD. You've got it at 21 vs 25 for my strap.

Can anyone suggest any more improvements? My Sapphire Rx470 seems to have a hard limit of 2100 for the memory clock. Setting the memory clock to 2150 in the BIOS, and increasing Powerplay Max Mem Freq table from 2100 to 2150 shows the change in pp_dpm_mclk, but the hashrate doesn't change. With the mclk set back to 2100, I dropped RAS2RAS from 157 to 150, but don't see any change in hashrate.

nerdralph

sr. member

Activity: 588

Merit: 251

Quote from: laik2 on March 22, 2017, 05:29:27 PM

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

You've got tRCDW(A) at 14 instead of 16, which shouldn't make any difference at all with ETH since it's all DAG reads. The tighter R2W and RP_WRA shouldn't make a difference for the same reason. Looser timing for RP_RDA (12 vs 11) might help stability, but I'm not having any stability problems. After 3 hrs of ETH mining at 28.3Mh, sgminer is showing just 45 HW errors.

update:
I tried tRC = 62 instead of 73, and got no speed increase (and then crash). I tried RCDR(A)=22 instead of 24, and got no increase in speed but a big increase in errors. So then I tried yours and I get a slight increase (~28.4 vs 28.3).

update2:
It looks like the performance increase comes from ARB_DRAM_TIMING.ACTRD. You've got it at 21 vs 25 for my strap.

laik2

sr. member

Activity: 652

Merit: 266

Quote from: nerdralph on March 22, 2017, 05:21:51 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done

Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

nerdralph

sr. member

Activity: 588

Merit: 251

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0. It's stable at 2100 on my Sapphire Rx470. The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000. I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Truthchanter

sr. member

Activity: 689

Merit: 253

Quote from: Eliovp on March 22, 2017, 04:48:57 PM

Quote from: Truthchanter on March 22, 2017, 04:40:17 PM

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

I posted a basic mod for Elpida And Hynix a few pages back..

Very much appreciated, Thank you!

laik2

sr. member

Activity: 652

Merit: 266

Quote from: nerdralph on March 22, 2017, 01:57:50 PM

Quote from: laik2 on March 22, 2017, 09:38:14 AM

Quote from: nerdralph on March 22, 2017, 09:10:26 AM

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes). Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 3, CL = 22, TM = 0, WR = 23, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

Quote

--> MC_SEQ_MISC1
-- MR0
   WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
   DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
   RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0

I think you are off by +1 with the MR0 CAS latency. SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

This is the tricky part, that's why the numbers don't fit

-- MR8
CLEHF = 1, WREHF = 1, RFU = 0, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0

Topic: Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED - page 43. (Read 155645 times)