Topic: DIY FPGA Mining rig for any algorithm with fast ROI - page 74. (Read 99472 times)

That's a good point, but the FPGA market looks totally dis-functional to me. I suspect that pricing practices will change as the impact of the Intel/Altera acquisition works thru the system.

After seeing posts saying someone fried an AWS F1 board with 300A, and that now there is a 150W limit but it is only a warning, I did a little searching and found that it appears AWS F1 limits your core power (Vccint) to 85W, which would be 100A at 0.85V.  They say they may/will shut you down (gate your clocks) if you exceed this, see https://github.com/aws/aws-fpga/blob/master/hdk/docs/afi_power.md

Also, someone suggested that since the power supplies are current limited, you could just raise the voltage to lower the current, unfortunately this is not how these chips work.  They basically take the same amount of current to do a given job, regardless of voltage.  So the lower the voltage, the lower the power.  This is why chip makers keep trying to run at lower and lower voltages, since it saves power.  

There is another power consideration in all these latest generation chips as well, which is static power (as opposed to dynamic), which is due to leakage in the transistors.  While dynamic power is linear with voltage, static power (leakage) is non-linear, going up as the square of voltage.  It also increases dramatically with temperature.  Static power in general has nothing to do with how much work is being done, hence the name "static".

Note that raising voltage may make you be able to run faster, but faster means yet more power, since dynamic power is highly dependent on clock rate.  You can run certain VU9Ps at 0.72V instead of 0.85V and this will certainly lower your power BUT it also kills your performance by 20-30%.  You can also run certain VU9Ps at 0.9V and get higher performance, with the associated higher power.  Of course the chip vendors charge a premium for these special devices over the standard ones.

So, determining the optimal combination of FPGA size, core voltage, and clock rate is not such a simple task.  As mentioned, we are working with the OP on this.

I think you are not factoring in the cost of FPGAs.

I looked at x16r / RVN numbers. I estimate about 25$ / FPGA with 10000 on the network. The 5+ months to recover cost. And ten 10000 is conservative, considering x16R has probably 4 times the GPUs on it currently compared to Phi.

Make 20000, and its down to $12/card.

Anyway its in motion, this is not going to end well for GPUs or FPGAs.

No. We'll see adaptive algos introduced which favor FPGA's. While FPGA programming may be a specialized skill and it takes time to code up a new algo, the cost and time to market of a FPGA solution will always be a lot less than designing and deploying new ASIC solutions and their energy efficiency (operational cost) will always be better than gpus.

Personally, I think there is no reason why fpgas can't be game changers.

You will have to design it yourself and here's a good place to begin:
https://github.com/aws/aws-fpga

I'm wanting to try fpga mining on an AWS EC2 instance.  It seems anyone that has done/is doing that is keeping the 'how to' close to their chest.  BFGMiner seems to be the way to go, but where does one get the bitstream (or in the case of AWS the AFI containing the bitstream)?

Drops the mic!

Thanks for spelling it out for these folks

BR

Actually it's not a silly question and you're not incorrect. You most likely will require a different bitstream for each board even though the Xilinx chip is the same. The reason for this is that the IO pins on the device are also configurable (i.e. you can change, within certain limits, which pins are connected to which external signals) and it is likely that the pins on the device have been connected up differently on each board. This may be a case of a simple recompile with no changes to the code but if the pinout is radially different you may have to reoptimise some of the timing to account for the differences in propagation delays between the pins and the logic.

This is a mutually-assured-destruction arms race.

I calculated for Phi, if there are 5000 such cards online, the per day return will be $12 per card and not $57. (The GPUs will make pennies, meanwhile.). That will be an year to get back cost at $4000.

And 5000 is conservative number I think, for one Algo.

Edit: And the irony of this -> Only ASICs will survive.

Don't worry there is no last chance in an arms race, except when everything blows up. They will just come back with a  bigger/better bomb.

Is this last chance for Xilinx to cash-out some high-priced FPGA volume before Intel makes available to public XEON-FPGA single chip? Second half of this year as announced.

  ok now i see. sorry for my noob question.

they use the same xilinx chip.

Im a little confused with the OP's suggestions. In the first post he clearly recommends the Xilinx VCU1525 but later on, throughout the thread, he shows his preferences for the Bittware XUPP3R-VU9P.

Surely the bitstream will be chip-specific so if that is the case then he or someone will have to "compile" a bitstream for each device. And as he seems to be working more closely with Bittware that will take preference.

The Xilinx DK-U1-VCU1525-A-G is a dev board and locally the price is very high. If I need to buy two to run one also but the OP preference is Bittware then that Is a sizeable investment to risk. I really think that this will change the face of Altcoins but we will need more bitstream developers.

As said before we need the Clyamores/Wolfs of FPGA's and Open Hardware design.

not as a fast but not so far away FOR THE SAME COST, people need to read better, i was not talking 1vs1

unless you think that a 1180 will cost $4000...

The famous "take a plane and let's have a beer" scam ! what a pity !!!

What is hoped to be accomplished with HBM/HBC? What algorithms ? These typically offer in the order of 500GB/s. That means for ETH they support a max of 62MH, and for CN7 they alone support “only” 16KH, but they add huge cost premiums to FPGAs, and offer no advantage over GPUs.

The FPGA advantage is in calculation bound code, or algorithms whose work happens in memory spaces < 40MB or so, where the onboard 11+ TB/s of ultraram/BRAM can be used.

External QDR is going to top out at 80-160 GB/s too because of pin count. Sure it is low latency but that is only part of the equation.

The absolute most bandwidth you can get off chip is if you used 128 32 GBit/s transceivers in a very expensive chip, and that will give you... 512 GByte/second again.

There’s little to be gained with off chip memory of the very expensive variety, in most cases.

HMC is usually soldered on to the board just like HBM.  HMC can provide staggering amount of bandwidth although it suffers in latency.  Uses SERDES communication.
There are HMC+Altera FPGA paired boards by PicoComputing iirc.

What is the best 64GB DDR4 Ram to get for the VCU1525 then?

No, a new board would have to be designed.