Topic: DIY PCB with AVALON: "The Quarter Stick" - Needs Help! - page 11. (Read 89446 times)

Sexy I am refreshing your git already

I've heard of people doing that but I don't have the stomach for it myself. I have used water cooling on some old socket 478 mainboards and I still have 3 water blocks from this. They actually may work for this but I probably won't bother. Well, maybe, but don't know. My mini-ITX Core2Duo dissipates 30W in one spot and works with a small fan. I'm reasonably confident that spread over 16 chips, 80 cm2 of copper, and heat sinks, the same heat output can be handled by heat sinks and air flow. (I really need one of these IR temperature guns though.)

The whole non-chip side of the board will be a big GND plane that mates directly with 2 heat sinks. I can't put anything there except around the edges and up the middle between heat sinks. I expect all caps to be on top and all are ceramic anyway. Just one 12V input electrolytic to go next to power connector. My plan is to bring the 1.2V down each side to the chips and run all the data lines up the middle. By having a centre channel between 2 heat sinks on back I can place the PIC and oscillator there and use both layers for vias. I can't run vias under the heat sink. Well, this what I'm thinking right now.

BkkCoins,

Thank you for your prompt reply! I will watch your git very closely:)

Another cooling idea. If you can design the PCB so all capacitors to be on top. We can submerge it in mineral/transformer oil and it will cool the chips down nicely. The option not to submerge capacitors will be great. As far as i know they are the only ones where rubber can be damaged from oil. The pcb to be partially submerged all asic chips and oil not to reach the capacitors
What about it?
Best

I'm aware of this but I think with a bundle of thermal vias under the pad the heat will be conducted directly to the heat sink on back. The FR4 material is a poor heat conductor so I can't see the internal layers really dissipating much in comparison. Without the big heat sink it would definitely be a problem and the internal layers would help. To be honest I'm not sure but I think it is worth trying. My theory is that getting the heat directly to the heat sink is better than counting on dissipation thru internal layers. I thought about using thinner FR4 material as well since that would give better heat conduction.

A 4 layer board would be more typical. I think that the specifics of this case merit looking at a 2 layer one. Not high frequencies and relatively few signals make a case for trying. If the routing ends up being too difficult I would backtrack to a 4 layer design. We'll see.

I have some MicroFit Jr connectors on hand for power (I like the small size) but I'm thinking I should use the standard MiniFit PCIe connectors. They're somewhat bigger. The adapters and Y connectors are so common it would make hooking up lots of boards very easy. For the MicroFitJr I would have to make special Y cables - kind of a hassle.

Interesting. I was just guessing so I'm eagerly awaiting the docs.
I didn't even think about likelihood of collision but you're right. Though you also have to account for the timing as the serial data is 112500 baud compared to the hashing at 282 MH/s. So a lot of hashes are done during the time of 32 bits shifted out. Roughly 2500 x 9 chips. Well, still slim odds.

Here's another interpretation: each of those 2 byte register values can be interpreted as a little-endian integer, with bits 4 - 11 giving the core clock rate in 2 MHz increments. I would hypothesise that the 32 MHz clock is being pre-divided by 16, then multiplied by the factor given in this register. If that's true, it should be possible to tweak the clock rate in 2 MHz increments. If any of these DIY boards have a programmable power supply, then it could be just like the GPU days, with people tweaking their boards to get that extra few percent.

(As for why the clock isn't just 2 MHz to begin with, perhaps the 32 MHz is also used as a serial clock.)


The probability of two (or more) ASICs in a set of 10 hitting a valid nonce at the same time is about 2e-18. You could OR together all 10 outputs, ignore collisions, and get away with it (you'll lose a negligible portion of valid results).

BkkCoins ,

Do you think that  2 layers PCb would be ok. As far as i understand 4 layers PCb is used because of chip cooling. PCB is used for cooling also

Otherwise your design looks perfect, just put a molex for 12V from PSu and we are ready to rock!

Much thanks. I'll definitely keep an eye on your Github account. :-)

The design I'm working on is 16 chips on a 10cm x 8cm board. Each board has a PIC USB controller but also supports I2C. This allows chaining multiple boards together so they use only one USB port. I'm targeting a 2 layer board to keep costs very low. If I run into problems with 2 layers then I'll bump up to 4 layer but that increases pcb cost by 3-4x. Right now parts cost estimate for one board is about $20 including pcb, not including ASIC, heat sink, assembly or parts shpg. ($20/16 chips is $1.25 per chip.)

I'll post my design on github eventually after final specs come out. You could panelize 8 boards on a larger 20cm x 32cm pcb for production. Then you would have 4 BIG boards total. Or whatever combination works. On each panel you would tie the sections together with I2C bus (4-wire ribbon cable), have one USB port and make a power splitter lead to distribute the 12V. 8 units using 32W each is 256W per BIG board. You could run two boards off a good 650W supply. Smaller boards give a bit more flexibility in arranging them for cooling.

I'll post more as I progress or check here:  http://github/bkkcoins
Don't expect anything until after Avalon docs are released.

A great work! But it's too complicated for me, but I will continue to pay attention to it.

Are there any plans to make a larger miner PCB design? I have about 480 chips on the way, but no knowledge of EE. I'm hoping for something I can take to a local plant for printing and assembly, but the aim as stated in the amended OP would result in too small of a board. I don't have 480 USB ports available... 

In that article the Avalon being referred to is the bus protocol used by the Altera NIOS II microprocessor core. Nothing to do with the mining machine named Avalon.

As for how "our" Avalon communicates I haven't found that info yet and it may be I2C but it's not the only standard around. It could be simply serial (using an USART), or SPI or CAN bus (unlikely), or proprietary or who knows.

I favour it being a simple serial daisy chain. In that case the FPGA does very little except act as a traffic switch between the FTDI USB-Serial converter and the final selected chip sub-module. The first N bits shift into a path selector register and choose the output path for the remaining M bits. But I'm guessing. For all I know there's a microprocessor core in the FPGA making decisions and using I2C to each ASIC. I2C is a more complicated protocol that requires an I2C core or micro-controller.

The serial data sent by the driver contains a few bytes of header data for each job. miner number and asic number are part of this. Miner number would select the route to a sub-module. Avalon has 24 miners and 10 chips per miner. Since it sends this data for each job and not once at startup we can likely assume it doesn't have "intelligence" on board. Just something to route work data to each chip.

The driver sends all 10 chips work data for each job enumerated out as a long stream. This seems to point at it being ready to be fed into a long shift register chain spanning the 10 chips.

I know about the "coincidental" name, but certainly that design seem quite standard. So, how does the Spartan-6 (FPGA) controller communicate with the Avalons, if they're not using I2C?

No, just a coincidental use of the same name.

Is the Avalon design related to this?

I have to discuss it with my partners but what I can commit to do in the meantime is that as soon as I have the broken Avalon in my power I will send pictures of every little corner so we can collectively understand how is built.

Also we have bought 10K of chips to build ASIC miners and would be glad to include an EE in our project if he can help us speed up the time to market of the machines.

All the best,
Dieguito   

Great work, could some Avalon owner send us a picture of the back of the PCB?

Would you consider selling one of the hashing submodules out of it (one of the boards with the 10 ASIC chips)?

I would love to have one on hand to study also.

Yes, this is correct. I mentioned it back up the thread a ways. Most likely there is a PLL on the ASIC as none of the chips on board seem to be right for this (and if there was one it would be best close to the ASICs).

The cgminer driver for Avalon sets the frequency as part of the prep for each work sent so I expect that it gets shifted into the device via the serial, just before the actual work data. It seems to be a couple bytes so presumably there is a PLL register controlling frequency.

Here are the register values:

256 MHz: 0x03 0x08
270 MHz: 0x73 0x08
282 MHz: 0xd3 0x08
300 Mhz: 0x63 0x09

edit: A bit of pondering over the numbers...

Second byte is multiplier 0x08 * 32 = 256
First byte, low bits 3 is constant so probably sets something up, mode or ?.
The first byte, high bits are half of the offset added to the second byte. Not sure how that works but it does.

256 = 0*2 + 8 * 32
270 = 7*2 + 8 * 32
282 = d*2 + 8 * 32
300 = 6*2 + 9 * 32

So setting, 0xf3 0x08 should give 286 MHz.

Ah, new information (to me)! This is very helpful.

I'm usually not one to speculate on such things as a chip pinout, but allten seemed eager to have more information, perhaps to move a little further on his pcb layout.

I'll agree the top pour has to be Vcor, and that 7,24,37 are most likely Vio.


I spy with my little eye, an XO! On the card, look at the space below the backplane connector. There is a metal can smt chip that has the writing "TXC 32.0 CBB3V" on it. Looks an awful lot like:
http://www.txccrystal.com/images/pdf/7w.pdf

If it is indeed a 32MHz signal, that would support my idea of single ended clock lines (pushed by the little 6-pin buffer lookin' guy below the xo).