Sorry wish I had more info.
I think the 20 pin connector on the ASIC module connects into a backplane.
The backplane collects the I/O signals from the 8 modules into a 40 pin ribbon connector.
The backplane also distributes power to the modules.
Would be nice to have the pin out for the 20 pin connector.
Hope someone sends you a broken module.
Topic: DIY PCB with AVALON: "The Quarter Stick" - Needs Help! - page 7. (Read 89444 times)
Can you forward me the link to the Avalon page?
https://en.bitcoin.it/wiki/Avalon#Chip_Specification
Quote
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
Oh! OK, Thank you!
I have visited it a few times, I thought you were referencing some additional information.
Anyway, tomorrow is May 1st, Will Avalon release the reference design as promised?
The link to the Avalon wiki is
https://en.bitcoin.it/wiki/Avalon
https://en.bitcoin.it/wiki/Avalon
Can you forward me the link to the Avalon page?
https://en.bitcoin.it/wiki/Avalon#Chip_Specification
Quote
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
BitSyncom,
Have fun working on documentation, it sure is fun, fun, fun...
I'm willing to voluntarily contribute if you require additional help, ie, building a website with schematics and diy flow?
Have fun working on documentation, it sure is fun, fun, fun...
I'm willing to voluntarily contribute if you require additional help, ie, building a website with schematics and diy flow?
A website would be awesome! Do you have server hosting already available that could be utilized?
We need to come up with a good name for this.
Here's my first pitch: Avalon + Jalepeno = Javal
I'd keep any BFL references out of it.
Nice work!
The Avalon page says the ASIC has 2 serial bypass outputs.
Do you think the bypass signals leave the 10 chip module or just connect between ASIC chips.
Also could one serial path be used for passing data and the other for controlling the ASIC?
I didn't know about the bypass signals, but everything makes sense, two data lines per section, 8 sections totaling 16 lines to the FPGA controller board…The Avalon page says the ASIC has 2 serial bypass outputs.
Do you think the bypass signals leave the 10 chip module or just connect between ASIC chips.
Also could one serial path be used for passing data and the other for controlling the ASIC?
Can you forward me the link to the Avalon page?
I think that the bypass signals leave the board. Every ASIC would be listening to the network (bypass signals) and requesting permission (i.e. bringing the line to a logic "0") to send when needed. This is actually no difficult to implement.
At this point I am just guessing.
This is the actual circuit from the Avalon board. I think that all the data lines for the 10 chips are tied in parallel (hence the drivers). There should be a few chip select address lines going into each section. If the data out are 3-state, I don't see any conflict or line overload.
Actually, I don't have a board in my hands, if I had, the full diagram would be complete by now and I would be finishing my version.
There is not need for ultrasound or any other (x-rays...?) technique. With a physical board I can finish the capture swiftly.
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Actually, I don't have a board in my hands, if I had, the full diagram would be complete by now and I would be finishing my version.
There is not need for ultrasound or any other (x-rays...?) technique. With a physical board I can finish the capture swiftly.
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Where are you located BitHav? Would detailed pictures from the boards or RX help?
All the best,
Dieguito
I am located in Florida.
Yes, any bit of info will help. A real board (even incomplete or defective) will be even more helpful. Need to determine not just connections, but component values as well.
Nice work!
The Avalon page says the ASIC has 2 serial bypass outputs.
Do you think the bypass signals leave the 10 chip module or just connect between ASIC chips.
Also could one serial path be used for passing data and the other for controlling the ASIC?
The Avalon page says the ASIC has 2 serial bypass outputs.
Do you think the bypass signals leave the 10 chip module or just connect between ASIC chips.
Also could one serial path be used for passing data and the other for controlling the ASIC?
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Someone did post further up this thread that they had a broken board and wanted to help with figuring out the details.That was me BkkCoins
This is the actual circuit from the Avalon board. I think that all the data lines for the 10 chips are tied in parallel (hence the drivers). There should be a few chip select address lines going into each section. If the data out are 3-state, I don't see any conflict or line overload.
Actually, I don't have a board in my hands, if I had, the full diagram would be complete by now and I would be finishing my version.
There is not need for ultrasound or any other (x-rays...?) technique. With a physical board I can finish the capture swiftly.
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Actually, I don't have a board in my hands, if I had, the full diagram would be complete by now and I would be finishing my version.
There is not need for ultrasound or any other (x-rays...?) technique. With a physical board I can finish the capture swiftly.
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Where are you located BitHav? Would detailed pictures from the boards or RX help?
All the best,
Dieguito
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Someone did post further up this thread that they had a broken board and wanted to help with figuring out the details. A pre-Drawing of the Power Block Section of the Avalon Project
Is this your design or something you reversed from the Avalon board?If we know that only 2 data lines go off the module then that helps nail down something about how output data is handled.
Reversed from the Avalon board
Excellent work!!
This is the actual circuit from the Avalon board. I think that all the data lines for the 10 chips are tied in parallel (hence the drivers). There should be a few chip select address lines going into each section. If the data out are three states, I don't see any conflict or line overload.
I guess tristate outputs would work fine. The chances of two boards posting results at the same time is quite small and a collision likely wouldn't cause damage beyond corrupt data.I don't think the inputs run to chips in parallel judging by the cgminer driver code which sends a long stream of start values one per chip in sequence. Also, we don't see any method of selecting chips based on the chip info provided. I believe the BYPASS pins are the end of each input shift register in the ASIC. So they get tied to the next ASIC and allow shifting in one long 320 bit work start sequence. I'm also basing this on the Icarus chip he did before which had this type of idea in the hdl code but was limited to the two chips on board. But ya, I'm just guessing for now.
A pre-Drawing of the Power Block Section of the Avalon Project
Is this your design or something you reversed from the Avalon board?If we know that only 2 data lines go off the module then that helps nail down something about how output data is handled.
Reversed from the Avalon board
I'm happy to see that all 10 outputs are not sent off board. Must be they're wire OR'd. You didn't see a pull-up resistor on the data lines coming from the ASICs? Also, any guess as to whether the pairs of data are for two separate hash engines or are CLK+DAT for one engine? Though I wouldn't expect a CLK out for the data out, so it seems more likey there are two simple uart style serial chains.
@secretmike, I think you mean 5 and 5? I would guess yes. Trying to push all 10 with one line could cause signal issues due to line capacitance.
edit: I wonder if an ultrasound unit would show the internal traces?
Actually, I don't have a board in my hands, if I had, the full diagram would be complete by now and I would be finishing my version.
There is not need for ultrasound or any other (x-rays...?) technique. With a physical board I can finish the capture swiftly.
Doe anybody have a broken board to lend? After a week I will return it fixed for free as a gesture of gratitude (except for the ASIC chips that still are not available).
Reversed from the Avalon board
@secretmike, I think you mean 5 and 5? I would guess yes. Trying to push all 10 with one line could cause signal issues due to line capacitance.
Right sorry, 5 and 5.
Can you tell if the asic data signals are daisy-chained together? [input buffer] -> 1 -> 2 -> 3 -> ... -> 10 -> [output buffer]
Thanks, this is super helpful!
A pre-Drawing of the Power Block Section of the Avalon Project
Is this your design or something you reversed from the Avalon board?If we know that only 2 data lines go off the module then that helps nail down something about how output data is handled.
Reversed from the Avalon board
I'm happy to see that all 10 outputs are not sent off board. Must be they're wire OR'd. You didn't see a pull-up resistor on the data lines coming from the ASICs? Also, any guess as to whether the pairs of data are for two separate hash engines or are CLK+DAT for one engine? Though I wouldn't expect a CLK out for the data out, so it seems more likey there are two simple uart style serial chains.
@secretmike, I think you mean 5 and 5? I would guess yes. Trying to push all 10 with one line could cause signal issues due to line capacitance.
edit: I wonder if an ultrasound unit would show the internal traces?
A pre-Drawing of the Power Block Section of the Avalon Project
Is this your design or something you reversed from the Avalon board?If we know that only 2 data lines go off the module then that helps nail down something about how output data is handled.
Reversed from the Avalon board
Interesting - so does the clock driver have one line go to 4 chips and the other line to the other 4?
A pre-Drawing of the Power Block Section of the Avalon Project
Is this your design or something you reversed from the Avalon board?If we know that only 2 data lines go off the module then that helps nail down something about how output data is handled.
Reversed from the Avalon board
A pre-Drawing of the Power Block Section of the Avalon Project
Is this your design or something you reversed from the Avalon board?If we know that only 2 data lines go off the module then that helps nail down something about how output data is handled.
A pre-Drawing of the Power Block Section of the Avalon Project
(including the clock source and distribution and data buffers)
Some values still to define. Some components (just a few) in the circuit are placeholders (known footprint but unknown values).
The FB resistor of the Buck converter needs adjustment.
Q5 is not populated in the board, so the converter is enabled by default.
(including the clock source and distribution and data buffers)
Some values still to define. Some components (just a few) in the circuit are placeholders (known footprint but unknown values).
The FB resistor of the Buck converter needs adjustment.
Q5 is not populated in the board, so the converter is enabled by default.
Jump to: