First let me say, I'm glad you released this 
It's nice to see others working on designs and sharing them (even if they may not be perfect lol).
I also like the super "spartan" approach (minimal board, modular via backplane and so on). It's similar to an approach I'm taking in my own design.
I haven't looked at the PCB/Schematic in detail, though at first glance I suspect the following will be big issues:
- Your FPGAs are pretty close together. Judging from the cooling needed on other designs (on both the back of the PCB and the chip via heatsink) you're going to need more space between them. But that's just first impression.
- It looks like you're only using 0.1 DIL headers for the backplane? and if so you're only using 2 pins per power line? I'm a bit concerned about the current you're jamming through those pins. (and relatively small traces). Remember that a mining FPGA can draw upwards of 10W per chip (I realize that's divided across the power lines, but VCCINT will take the brunt of it)
- Can your voltage regulators handle the draw from all 4 FPGAs? (it does look like your VCCINT reg is rated for 40A which should handle it, but to be considered. Also are you isolating powerline noise well enough between FPGAs?
I personally hope this design works out well, just throwing some feedback out there
It's nice to see others working on designs and sharing them (even if they may not be perfect lol).
I also like the super "spartan" approach (minimal board, modular via backplane and so on). It's similar to an approach I'm taking in my own design.
I haven't looked at the PCB/Schematic in detail, though at first glance I suspect the following will be big issues:
- Your FPGAs are pretty close together. Judging from the cooling needed on other designs (on both the back of the PCB and the chip via heatsink) you're going to need more space between them. But that's just first impression.
- It looks like you're only using 0.1 DIL headers for the backplane? and if so you're only using 2 pins per power line? I'm a bit concerned about the current you're jamming through those pins. (and relatively small traces). Remember that a mining FPGA can draw upwards of 10W per chip (I realize that's divided across the power lines, but VCCINT will take the brunt of it)
- Can your voltage regulators handle the draw from all 4 FPGAs? (it does look like your VCCINT reg is rated for 40A which should handle it, but to be considered. Also are you isolating powerline noise well enough between FPGAs?
I personally hope this design works out well, just throwing some feedback out there
The connectors in the 3d renders arnt the actual ones in using. I'm using these:
http://search.digikey.com/us/en/products/15-24-7160/WM17742-ND/1633805
these connecters can handle alot more than im putting through it and VCCINT gets 4 pins VCCIO gets 4 pins Ground gets 4 pins and the last 4 are for jtag
also look at my update in the post about the power supply 40 watts at 1.2v is around 33 amps
and regarding noise I'm following all the guidelines in the Spartan 6 PCB and pin planning guide on using low esr capacitors
I do think the cooling may be a problem though it might be good to space them out a bit more they are spaced a inch apart
EDIT:
Btw my power traces are huge lol I dont think you noticed but check out this pic of the bottom of the board
http://img268.imageshack.us/img268/6672/eagleuptestboardbottom.png
