Community: "just doubled the hashrate, easy as cake"
Topic: Fury/Blizzard tuning and mods - page 37. (Read 115281 times)
ASIC fabs: "ok, thats the max we can get, begin selling"
Community: "just doubled the hashrate, easy as cake"
Community: "just doubled the hashrate, easy as cake"
Re: changing the baud rate in cgminer/bfgminer
It looks like windows is easy, just change ICARUS_IO_SPEED or ZEUS_IO_SPEED (depending on which version you're using) and recompile.
Linux is more tricky ...
For cgminer, the available speeds are hard coded in serial_open() in fpga_utils.c eg
case 115200:
cfsetispeed(&my_termios, B115200);
cfsetospeed(&my_termios, B115200);
So you'll need to add the new speed there, but it must be one of the ones supported. In raspi I think these come from /usr/include/asm-generic/termbits.h and it looks like it's the next one after B115200 is B230400, though there is also BOTHER (I don't know how that works).
Bfgminer is even more confusing. The baud rate is defined in lowl_vcom.c via tiospeed_t() and a macro IOSPEED, but it's not obvious where the choices are defined (iospeeds_local.h does not seem to exist). It's probably the same range as for cgminer though. The upside is that it probably doesn't need any coding, just change the ZEUS_IO_SPEED as in windows.
Anyway that's as far as I can go with this (I don't have any zeus hardware myself to play with, I decided not to take a punt on this race
). Best of luck (and please don't blame me if you fry your board 
).
It looks like windows is easy, just change ICARUS_IO_SPEED or ZEUS_IO_SPEED (depending on which version you're using) and recompile.
Linux is more tricky ...
For cgminer, the available speeds are hard coded in serial_open() in fpga_utils.c eg
case 115200:
cfsetispeed(&my_termios, B115200);
cfsetospeed(&my_termios, B115200);
So you'll need to add the new speed there, but it must be one of the ones supported. In raspi I think these come from /usr/include/asm-generic/termbits.h and it looks like it's the next one after B115200 is B230400, though there is also BOTHER (I don't know how that works).
Bfgminer is even more confusing. The baud rate is defined in lowl_vcom.c via tiospeed_t() and a macro IOSPEED, but it's not obvious where the choices are defined (iospeeds_local.h does not seem to exist). It's probably the same range as for cgminer though. The upside is that it probably doesn't need any coding, just change the ZEUS_IO_SPEED as in windows.
Anyway that's as far as I can go with this (I don't have any zeus hardware myself to play with, I decided not to take a punt on this race
). Best of luck (and please don't blame me if you fry your board ).
Hi all,
some guys of the litecointalk.org forum pointed to your great topic. So as I think you have some requirements to be reflected by my BFGminer port I come over to collect them.
And here I am. So first thing you like to remove the clock speed barrier right?
Some addendum to the initial posting:
> Tech Topic for the BFGminer port opened yesterday: https://litecointalk.org/index.php?topic=20477.0
> Link to Sources: https://mega.co.nz/#F!DRE0EDCK!aPxX5hZ2S_2UBTA14sU3ow
> Regarding Minepeon you can set me as one of the contact persons, as I am working with Neil and I am one of the technical responsibilities in the according forum: http://minepeon.com/forums/index.php
Regards
Darkwinde
some guys of the litecointalk.org forum pointed to your great topic. So as I think you have some requirements to be reflected by my BFGminer port I come over to collect them.
And here I am. So first thing you like to remove the clock speed barrier right?
Some addendum to the initial posting:
> Tech Topic for the BFGminer port opened yesterday: https://litecointalk.org/index.php?topic=20477.0
> Link to Sources: https://mega.co.nz/#F!DRE0EDCK!aPxX5hZ2S_2UBTA14sU3ow
> Regarding Minepeon you can set me as one of the contact persons, as I am working with Neil and I am one of the technical responsibilities in the according forum: http://minepeon.com/forums/index.php
Regards
Darkwinde
64Mhz crystal would give 230400 and setting the ltcclk to 200 should have similar performances as 400 clk with 32Mhz.
But doubling the core frequency might be way too much
42.2Mhz would be nice.
25% increase and 153600 baud rate.
But doubling the core frequency might be way too much
42.2Mhz would be nice.
25% increase and 153600 baud rate.
It may be OK, depends on how sensitive the asic PLL is to the reference clock. Worst case is that it fails to lock, but it will probably be fine. The 153600 baud rate may be more of a problem. You'll need to recompile cgminer/bfgminer and (as I mentioned above) linux seems restricted in the supported baud rates. Unfortunately compiling on windows is rather more of a pain than it is on linux. I'm still googling around to see what I can find, but I've got some chores to do this morning so I'm offline for a few hours now.
doesn't the CP2102 have its own internal 48Mhz clock?
It shouldn't be affected, but I never worked with this chip before.
or do you mean communication between the zeus chips and the CP2102?
It shouldn't be affected, but I never worked with this chip before.
or do you mean communication between the zeus chips and the CP2102?
Yes, the ASIC comms is hard coded as a specific fraction of the chip clock (115200 baud for the default crystal)
I've just edited my post above about possible baud rates. I don't know about windows, but linux is restricted. I did find this via google about modifying the driver, so there may be something that can be done.
I have some 25 and 27Mhz crystals available, I'll check first if it still works with either one.
Best case, the chips will run slower.
Worst case = no communication between the chips and the cp2102
64Mhz crystal would give 230400 and setting the ltcclk to 200 should have similar performances as 400 clk with 32Mhz.
But doubling the core frequency might be way too much
42.2Mhz would be nice.
25% increase and 153600 baud rate.
doesn't the CP2102 have its own internal 48Mhz clock?
It shouldn't be affected, but I never worked with this chip before.
or do you mean communication between the zeus chips and the CP2102?
It shouldn't be affected, but I never worked with this chip before.
or do you mean communication between the zeus chips and the CP2102?
Yes, the ASIC comms is hard coded as a specific fraction of the chip clock (115200 baud for the default crystal)
I've just edited my post above about possible baud rates. I don't know about windows, but linux is restricted. I did find this via google about modifying the driver, so there may be something that can be done.
in cgminer code, we have something similar
FF*3/2 is 382.5
and this
Quote
#if 1
if(opt_chip_clk>(0xff*3/2)){
opt_chip_clk = 0xff*3/2;
}
else if(opt_chip_clk<2){
opt_chip_clk = 2;
}
clk_reg= (uint32_t)(opt_chip_clk*2/3);
#endif
if(opt_chip_clk>(0xff*3/2)){
opt_chip_clk = 0xff*3/2;
}
else if(opt_chip_clk<2){
opt_chip_clk = 2;
}
clk_reg= (uint32_t)(opt_chip_clk*2/3);
#endif
FF*3/2 is 382.5
and this
Quote
golden_speed_percore = (((opt_chip_clk*2)/3)*1024)/8;
The clock speed is communicated to the zeus asic as an 8 bit value, max is 255 (it's scaled as 2/3 of the clock speed). There is no way you can set it any higher! (Addendum: beware that the max may actually be 254 in practice and 255 may be ignored, this was the behavior of the original FPGA code, and if zeus copied it unchanged then it would be the same here. It would be interesting to know if this is true or not
).If you're considering changing the clock crystal to get a faster base speed, then be aware that this will also change the baud speed of the serial interface. You will need to change the baud rate of the serial driver to match (115200 baud for the stock crystal).
doesn't the CP2102 have its own internal 48Mhz clock?
It shouldn't be affected, but I never worked with this chip before.
or do you mean communication between the zeus chips and the CP2102?
in cgminer code, we have something similar
FF*3/2 is 382.5
and this
Quote
#if 1
if(opt_chip_clk>(0xff*3/2)){
opt_chip_clk = 0xff*3/2;
}
else if(opt_chip_clk<2){
opt_chip_clk = 2;
}
clk_reg= (uint32_t)(opt_chip_clk*2/3);
#endif
if(opt_chip_clk>(0xff*3/2)){
opt_chip_clk = 0xff*3/2;
}
else if(opt_chip_clk<2){
opt_chip_clk = 2;
}
clk_reg= (uint32_t)(opt_chip_clk*2/3);
#endif
FF*3/2 is 382.5
and this
Quote
golden_speed_percore = (((opt_chip_clk*2)/3)*1024)/8;
The clock speed is communicated to the zeus asic as an 8 bit value, max is 255 (it's scaled as 2/3 of the clock speed). There is no way you can set it any higher! (Addendum: beware that the max may actually be 254 in practice and 255 may be ignored, this was the behavior of the original FPGA code, and if zeus copied it unchanged then it would be the same here. It would be interesting to know if this is true or not
).If you're considering changing the clock crystal to get a faster base speed, then be aware that this will also change the baud speed of the serial interface. You will need to change the baud rate of the serial driver to match (115200 baud for the stock crystal). This may be non-trivial! While the cp2109 usb-uart bridge supports higher baud rates (115200, 128000, 153600, 230400, 250000, 256000, 460800, 500000, 576000, 921600), linux seems to be restricted to just 230400 (I am not an expert though, seek a guru).
I measured Zeus R9 R10 R11 on my board
R11 is in the correct spot on my Week 1 GAW Fury
R9 measures 4.93K on the board
R10 measures 4.92K on the board
I checked like 5 times and cross checked my multimeter with several spare resistors.
R10 = ( R9 * Vfb ) / ( Vout - Vfb )
4.92 = ( 4.93 * 0.591 ) / ( 1.183v - 0.591 )
Looks like mine is slightly under volted at 1.183v (I did not measure the voltage)
I'll have to check my other Fury (Week 3).
edit:
Almost the same on the other Fury
R11 .906k
R10 4.91k
R9 4.91k
so 1.182v
R11 is in the correct spot on my Week 1 GAW Fury
R9 measures 4.93K on the board
R10 measures 4.92K on the board
I checked like 5 times and cross checked my multimeter with several spare resistors.
R10 = ( R9 * Vfb ) / ( Vout - Vfb )
4.92 = ( 4.93 * 0.591 ) / ( 1.183v - 0.591 )
Looks like mine is slightly under volted at 1.183v (I did not measure the voltage)
I'll have to check my other Fury (Week 3).
edit:
Almost the same on the other Fury
R11 .906k
R10 4.91k
R9 4.91k
so 1.182v
Seems like Chinese/Zeus documentation is as accurate as their implementation ...
ZiG
You will have to make measurements on components removed from the board. Read the value written on them. I'm almost sure you have 9.3k and 9.1k too.
Subbed, good stuff here.
Thanks...the company here is always creating only good stuff...
Subbed, good stuff here.
Remove the overclock limit? YES PLEASE!!!
cgminer or bfgminer...I don't care which.
although...it seems that bfgminer has a problem with manicminer pool for whatever reason. I can point bfgminer to nicehash and it works fine...point it to manicminer and it just sits at 0mhs.
cgminer or bfgminer...I don't care which.
although...it seems that bfgminer has a problem with manicminer pool for whatever reason. I can point bfgminer to nicehash and it works fine...point it to manicminer and it just sits at 0mhs.
Hey good work hardware side of things here! Hopefully you guys can do the same for the blades in the larger machines (they have the same voltage regulator chip so I'm assuming it will be very similar).
If you guys want ill take off the over clock limit on the driver.
If you guys want ill take off the over clock limit on the driver.
What are you waiting for, buddy...DO it... take the sucker off...I am just kidding...
Will be greatly appreciated...
ZiG
Hey good work hardware side of things here! Hopefully you guys can do the same for the blades in the larger machines (they have the same voltage regulator chip so I'm assuming it will be very similar).
If you guys want ill take off the over clock limit on the driver.
If you guys want ill take off the over clock limit on the driver.
The schematic was dated June 14 - printed on the pdf. I wonder if new miners will match it?
I measured Zeus R9 R10 R11 on my board
R11 is in the correct spot on my Week 1 GAW Fury
R9 measures 4.93K on the board
R10 measures 4.92K on the board
I checked like 5 times and cross checked my multimeter with several spare resistors.
R10 = ( R9 * Vfb ) / ( Vout - Vfb )
4.92 = ( 4.93 * 0.591 ) / ( 1.183v - 0.591 )
Looks like mine is slightly under volted at 1.183v (I did not measure the voltage)
I'll have to check my other Fury (Week 3).
edit:
Almost the same on the other Fury
R11 .906k
R10 4.91k
R9 4.91k
so 1.182v
R11 is in the correct spot on my Week 1 GAW Fury
R9 measures 4.93K on the board
R10 measures 4.92K on the board
I checked like 5 times and cross checked my multimeter with several spare resistors.
R10 = ( R9 * Vfb ) / ( Vout - Vfb )
4.92 = ( 4.93 * 0.591 ) / ( 1.183v - 0.591 )
Looks like mine is slightly under volted at 1.183v (I did not measure the voltage)
I'll have to check my other Fury (Week 3).
edit:
Almost the same on the other Fury
R11 .906k
R10 4.91k
R9 4.91k
so 1.182v
Seems like Chinese/Zeus documentation is as accurate as their implementation ...
ZiG
I measured Zeus R9 R10 R11 on my board
R11 is in the correct spot on my Week 1 GAW Fury
R9 measures 4.93K on the board
R10 measures 4.92K on the board
I checked like 5 times and cross checked my multimeter with several spare resistors.
R10 = ( R9 * Vfb ) / ( Vout - Vfb )
4.92 = ( 4.93 * 0.591 ) / ( 1.183v - 0.591 )
Looks like mine is slightly under volted at 1.183v (I did not measure the voltage)
I'll have to check my other Fury (Week 3).
edit:
Almost the same on the other Fury
R11 .906k
R10 4.91k
R9 4.91k
so 1.182v
R11 is in the correct spot on my Week 1 GAW Fury
R9 measures 4.93K on the board
R10 measures 4.92K on the board
I checked like 5 times and cross checked my multimeter with several spare resistors.
R10 = ( R9 * Vfb ) / ( Vout - Vfb )
4.92 = ( 4.93 * 0.591 ) / ( 1.183v - 0.591 )
Looks like mine is slightly under volted at 1.183v (I did not measure the voltage)
I'll have to check my other Fury (Week 3).
edit:
Almost the same on the other Fury
R11 .906k
R10 4.91k
R9 4.91k
so 1.182v
We're here to push the limits...we don't need no stinkin' safety measures! 
Probably coded in there as a safety measure. These chip use a lot of power and getter hotter the faster you run them. Imagine the power usage and heat coming off a War Machine with 256 chips if someone accidentally set the clk to like 828 instead of 328.
I'll hook the mini blades to the laptop I used when doing the first tests tomorrow.
I was using the windows build from Zeus.
We really need to remove this hardcap to take the full benefit of the overvolting.
5 hours hashing with 4 furys at 544 clock gives this
1000 / 30 Acc./Rej. 3.00 % rejection rate
44 Hardware errors
difficulty is 1920 at the moment
Pools reports 6Mh, sometimes almost 7Mh
I'm moving back to 381 during the night, just to check if anything changes.
I was using the windows build from Zeus.
We really need to remove this hardcap to take the full benefit of the overvolting.
5 hours hashing with 4 furys at 544 clock gives this
1000 / 30 Acc./Rej. 3.00 % rejection rate
44 Hardware errors
difficulty is 1920 at the moment
Pools reports 6Mh, sometimes almost 7Mh
I'm moving back to 381 during the night, just to check if anything changes.
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