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Topic: [In Dev] 28nm mining FPGA (Amateur) - page 4. (Read 8005 times)

sr. member
Activity: 322
Merit: 250
April 15, 2013, 05:30:47 PM
#3
interested!

please post pics + docs when you can!
full member
Activity: 126
Merit: 100
April 15, 2013, 01:56:28 PM
#2
Reserved
full member
Activity: 126
Merit: 100
April 15, 2013, 01:54:54 AM
#1
Hey all, this is just to let you know that me and a friend are working on making an FPGA miner using 2 Artix-7s. These are 50-65% more power efficient than the Spartan-6s, and faster as well. I'll do my best to keep this thread updated on where we are in the process. We will be using the open source FPGA miner (verilog port). Will try to optimize performance for the two chips
 
Neither of us have much experience with this, so it is kind of a learn as we go type of thing.
Have no fear, before releasing anything I am having professionals from Xilinx look at both hardware and software to make sure it is optimized.

Special thanks to iidx for helping out with the verilog.

April 14
I have the Xilinx software dev kit and an ML605, not much modification should be required for the Atrix-7 (there were no spare AC701s laying around so I can't be sure)
April 15
- Compiling the open source fpga miner is giving me some sort of translate error (it was made for spartan-6), Working on sorting that out.
- Thanks to fpgaminer I can safely estimate that this should put out about 1GH/s, probably a bit more.
- I (with help from iidx) have successfully compiled on the ML605, didn't have time to check out the actual hash it gets, but you have a good estimate now of what this FPGA will be able to get.
April 17
-Got a few of the hardware specs down
-Estimate a 5v supply will be used (still working on the power estimate)
-Estimated price is currently at ~250-300 USD per unit
October 6
-Project on hold
-So far mining software/hardware works (sort of)
-No idea when I will start this up again (school/work etc in the way)
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