Overclocking in General with my Small sample of 2 Units.
- I have good unit that has never performed better with different VID/PLL
- I have a defect unit that does about 1Ksol better at 185-195 VID. but its a poor example being defect.
Hi. dear friends. I have a problem in one of my chains in A9 zmaster. In order to fix it, I tried to decrease the voltage and frequency of my faulty board. but the main point is in there, whenever I try to decrease the T1Pll1 and T1VID1 options in config file, all of my chains frequency and voltage decrease at the same time. Look at my config file.
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After running this conf file, All of my chains frequency (pll) speed becomes 830 and their voltage (vid) set to 125.
Is there anyway to configure each chain's frequency and voltage separately? Is there anyone who test it before?
No, I could never get different VIDs for the boards. T1VID2/3 never did much for me. In the Newest firmware, it would change 'CGMiner-API stats' iVID value. I dont *think T1VID2/3 worked.. but I only messed around with it for a little bit b4 leaving it, getting wierd crashes the next day, and ditching the firmware. Its states in the Files, that T1VID sets the INITIAL voltage level, before tuning. However, When I use a higher VID I get a much higher power draw that stays. It honestly seems like there working on overclock. Just doesnt work. lol.
If you can read code you can get an idea of whats going on in these files.
https://github.com/ckolivas/cgminer/blob/master/driver-SPI-dragonmint-t1.chttps://github.com/ckolivas/cgminer/blob/master/dragonmint_t1.hThis i by no means easy to follow and on top of that, A9's seem to use this CGMiner Dragonmint Driver but with different values and who knows what other customization. ex. I cant find T1Adjust in these files. But for the most part, The process will be close or they wouldn't have used this code and started from scratch. Theres mention of logging about VID/Voltage/PLL(Mhz) in there that I dont see taking place. My guess is cgminer needs to be run in a debug mode. My fear is that inno commented it. The header file has clearly defined PLL tuning Min and Max. There's also ref_clk_khz and sys_clk_khz which I havent played with. No idea what they will adjust or are set at. Ive been avoiding hail marrys with such an expensive device.
--dragonmint-t1-options
Dragonmint T1 options ref_clk_khz:sys_clk_khz:spi_clk_khz:override_chip_num
About the other ports for the Hashboards. its a blur now but I think when I was running 2 boards it seemed like the ports needed to be utilized sequentially. Like I was using ports 1 and 3 and the board on 3 didnt work. Ive been using 1 and 2 when I remove a board ever since.
Im going to give those files another read when im rested, try some different cgminer debug modes and make sure I completely Probed the API. Dragonmint eventually was overclockable from what I read. So there's still figuring out how that worked and see if it applies to A9's. Squeezing this in between 14h nightshifts. This is probably all hard to read. Its time for some sleep.