Topic: Is an 80% decrease in power consumption possibe when going from 110nm to 65nm? (Read 3873 times)

Given avalon's actual 9.4 W/Gh power consumption, I really doubt BFL can even accomplish 3 W/Gh, let alone 1.

You might be right.
If power required for the greater frequency is the same, which I believe it's true at least for the dynamic power (1/2C*V^2*f + Qtransition*f), there is an efficiency increase. But you might be wright because at 65nm leakage power becomes comparable with dynamic power (unless you use LP process, which I doubt).  

EDIT: Looks like avalon falsified their real world numbers on their site, even after the fist machine was already in customers' hands. They updated them to "reflect customers' experience" to 620w for a 66Gh/s rig.

A smaller process might allow a higher frequency, but that won't increase efficiency.

There's an approximation of 110/65 = 1.69x reduction in linear dimensions which translates in shorter propagation time so greater maximum frequency. I know smaller the node, smaller the gain, but I'd say between these nodes (110 and 65mn) maybe there's a 1.3x speed gain. So, maybe a 2.86 x 1.3 = 3.7x only from "shrink". 

Comparing the squares of the process size should be a decent measure of efficiency, if everything else is similar. (110/65)^2 = 2.86x more efficient.  The rest of the advantage would come from a more efficient design.  If BFL's chips are "full custom" as they say, this could lead to additional gains over Avalon.

Comparing the squares of the process size should be a decent measure of efficiency, if everything else is similar. (110/65)^2 = 2.86x more efficient.  The rest of the advantage would come from a more efficient design.  If BFL's chips are "full custom" as they say, this could lead to additional gains over Avalon.

That'll be fine for most of their units, but the Mini-rig is already sitting at 1500w. Considering a standard wall plug is only good for 1650w, there's not much room for failure there.

That'll be fine for most of their units, but the Mini-rig is already sitting at 1500w. Considering a standard wall plug is only good for 1650w, there's not much room for failure there.

With real world inefficiencies, power consumption rising due to ambient temps, power supply inefficiency, and simple variance in chip yields I think they will underperform that number.  Note probably not 500MH/J vs 1000 MH/J but maybe 10% to 20% below.

Comparing the squares of the process size should be a decent measure of efficiency, if everything else is similar. (110/65)^2 = 2.86x more efficient.  The rest of the advantage would come from a more efficient design.  If BFL's chips are "full custom" as they say, this could lead to additional gains over Avalon.

The so-called tick-tock strategy is used by many chips manufactures as well (including AMD), you make it sound like its exclusively to Intel. No, it has nothing to do with AMD's failure.

dust got it right.  If it was exactly the same chip one would expect closer to 2x to 3x better efficiency.  A lot will depends on the exact design.  Personally I think Avalon went the right route.  Any ASIC is far superior to GPU so use 110nm, get a simple working design out the door.  A couple million in sales later you got plenty of money to do an improved design maybe tweak out 50% to 100% improvement in efficiency at the same 110nm, and THEN make a move to smaller process.  If your competitors are crushing you then you can either jump to 65nm or take a gamble on more efficient design AND a jump to 65nm on the same chip.  Get the most out of your resources and leave yourself options to improve.  Note this strategy is called tick-tock and is used by Intel.  Intel used it to good effect to utterly destroy AMD. 

Tick - do a die shrink
Tock - improve the efficiency (2nd gen design on same die size).

dust got it right.  If it was exactly the same chip one would expect closer to 2x to 3x better efficiency.  A lot will depends on the exact design.  Personally I think Avalon went the right route.  Any ASIC is far superior to GPU so use 110nm, get a simple working design out the door.  A couple million in sales later you got plenty of money to do an improved design maybe tweak out 50% to 100% improvement in efficiency at the same 110nm, and THEN make a move to smaller process.  If your competitors are crushing you then you can either jump to 65nm or take a gamble on more efficient design AND a jump to 65nm on the same chip.  Get the most out of your resources and leave yourself options to improve.  Note this strategy is called tick-tock and is used by Intel.  Intel used it to good effect to utterly destroy AMD. 

Tick - do a die shrink
Tock - improve the efficiency (2nd gen design on same die size).

For the record I don't think BFL is a "scam" but my guess is 1000 MH/J is the high end of their range.  With real world inefficiencies, power consumption rising due to ambient temps, power supply inefficiency, and simple variance in chip yields I think they will underperform that number.  Note probably not 500MH/J vs 1000 MH/J but maybe 10% to 20% below.

Note the following is a totally hypothetical example made up completely for my amusement.

Tick - 110nm Avalon (160 MH/J)
Tock - 110nm Improved Avalon (280 MH/J)
Tick - 65nm XXXX (560 MH/J)  <- improved avalon design die shrinked to 65nm
Tock - 65nm XXX (800 MH/J)  

I used to work at a tech company for a boss who was famous within the company for his slogan "Ship it!".  He'd say it, and we'd do it.

We shipped some hacked-together shit, and boy it's a good thing we did.  In retrospect, "ship it" was absolutely the right decision to have made every time.  It was far better to get something out the door that halfway worked, and to fix it better later than to delay and have nothing out there while we tried and tried again for perfection.

This went double for the confidence of our customers.  They by far preferred to see us doing something and getting something into their hands, even if it was hacked.