Klondike - 16 chip ASIC Open Source Board - Preliminary - page 74.

marto74

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Quote from: SebastianJu on July 09, 2013, 09:24:03 AM

Quote from: burnin on July 08, 2013, 09:44:58 PM

EMC-Lab confirmed the appointment.

And i have some more overclocking figures for you guys.
Note: I expect that future versions will be more stable due to a few changes.
341 Mhz 1.2V 57.5W - passed long term tests with 0.2% hw-errors.
409 Mhz 1.2V 68.04W - hw-errors increase to 3%
448 Mhz 1.2V 74.4W - not stable
448 Mhz 1.25V 81.6W - unstable 50% hw-errors
448 Mhz 1.28V 84.016W - unstable 50% hw-errors

Burnin made some overclocking tests, unfortunately without temperature. But maybe good for comparition.

Regarding the klondikes... will they have CE and other signs? Or should i ask the actual assembler for this?

CE mark is a test for safety.
It can be covered only with fully enclosed device.
The process of getting CE approval is quite time and money consuming ( at least 30-40 days) .

SebastianJu

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Quote from: burnin on July 08, 2013, 09:44:58 PM

EMC-Lab confirmed the appointment.

And i have some more overclocking figures for you guys.
Note: I expect that future versions will be more stable due to a few changes.
341 Mhz 1.2V 57.5W - passed long term tests with 0.2% hw-errors.
409 Mhz 1.2V 68.04W - hw-errors increase to 3%
448 Mhz 1.2V 74.4W - not stable
448 Mhz 1.25V 81.6W - unstable 50% hw-errors
448 Mhz 1.28V 84.016W - unstable 50% hw-errors

Burnin made some overclocking tests, unfortunately without temperature. But maybe good for comparition.

Regarding the klondikes... will they have CE and other signs? Or should i ask the actual assembler for this?

sensei

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Quote from: LaserHorse on July 09, 2013, 07:30:08 AM

Quote from: BkkCoins on July 09, 2013, 07:15:20 AM

Tell me about it. I have one planned but like the ceiling and floor it's on the waiting list. I'm sweating here most days but today was quite cool at 32C. We have 40C days here in March.

Good lord - i would in fact be dead and/or liquid!

Thanks for the pic - nice to solidify the image i had in my head Wink

When I was in Chongqing, China supporting the manufacturing plant I went out for a walk around town on a very rare off day. It was 42C and I was dyin'.

No wind either.

A relatively clear day for once.

LaserHorse

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Quote from: BkkCoins on July 09, 2013, 07:15:20 AM

Tell me about it. I have one planned but like the ceiling and floor it's on the waiting list. I'm sweating here most days but today was quite cool at 32C. We have 40C days here in March.

Good lord - i would in fact be dead and/or liquid!

Thanks for the pic - nice to solidify the image i had in my head Wink

Beastlymac

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Quote from: BkkCoins on July 09, 2013, 07:15:20 AM

I thought maybe people would like to see my Franken K...

80mm fan just connected to molex for now. See I caught the red led showing data xfer. The red GND lead off back is for scope probes (why isn't it black? just me being retarded.)

Heat sink not attched to fan, just sitting on top as I disconnect often to take it to the solder station.

Quote from: pixl8tr on July 09, 2013, 07:12:43 AM

Quote from: BkkCoins on July 09, 2013, 06:57:54 AM

Right now just on one side, U5,6,7,8 at 300MHz. I have to relocate my NOR gate hack board before I can put chips on the other bank. U8 seems to run a bit hotter than the others at 52C. Others <50C. With steamboats black heat sink and a fan the heat sink runs 37C (on that corner, barely warm to touch) in 32 ambient.

Great Job!!!!

BTW, "32 ambient" !!!!! LOL time for some AC.

Tell me about it. I have one planned but like the ceiling and floor it's on the waiting list. I'm sweating here most days but today was quite cool at 32C. We have 40C days here in March.

Looks good I can't wait to see the board fully populated

BkkCoins

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I thought maybe people would like to see my Franken K...

80mm fan just connected to molex for now. See I caught the red led showing data xfer. The red GND lead off back is for scope probes (why isn't it black? just me being retarded.)

Heat sink not attched to fan, just sitting on top as I disconnect often to take it to the solder station.

Quote from: pixl8tr on July 09, 2013, 07:12:43 AM

Quote from: BkkCoins on July 09, 2013, 06:57:54 AM

Right now just on one side, U5,6,7,8 at 300MHz. I have to relocate my NOR gate hack board before I can put chips on the other bank. U8 seems to run a bit hotter than the others at 52C. Others <50C. With steamboats black heat sink and a fan the heat sink runs 37C (on that corner, barely warm to touch) in 32 ambient.

Great Job!!!!

BTW, "32 ambient" !!!!! LOL time for some AC.

Tell me about it. I have one planned but like the ceiling and floor it's on the waiting list. I'm sweating here most days but today was quite cool at 32C. We have 40C days here in March.

pixl8tr

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Quote from: BkkCoins on July 09, 2013, 06:57:54 AM

Right now just on one side, U5,6,7,8 at 300MHz. I have to relocate my NOR gate hack board before I can put chips on the other bank. U8 seems to run a bit hotter than the others at 52C. Others <50C. With steamboats black heat sink and a fan the heat sink runs 37C (on that corner, barely warm to touch) in 32 ambient.

Great Job!!!!

BTW, "32 ambient" !!!!! LOL time for some AC.

Beastlymac

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Miner Setup And Reviews. WASP Rep.

Quote from: BkkCoins on July 09, 2013, 06:35:25 AM

Just started running with 4 chips. 17 WU/m, 1200 MH/s.

BkkCoins

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Quote from: kano on July 09, 2013, 06:42:10 AM

Quote from: BkkCoins on July 09, 2013, 06:23:56 AM

Quote from: kano on July 09, 2013, 05:33:00 AM

If you want the number of HW errors like you are counting, it is simply the device HW - NMW
Avalon device HW is bad nonces + NMW

No need to change anything.

What/where is NMW?

That's an Avalon added stat
(No Matching Work)
If your version of the code isn't adding HW but just calling submit_nonce() with each one, then the HW counter will just be the number of submitted that were no good (and Diff1 Work will be the number submitted - that includes HW)

Ok. I see. I only get NMW when it's hashing before any work is sent so I no longer have it send nonces when it's not in W (working) state. So when a flush occurs it changes to R (ready) state until new work is pushed. I was getting them at start up sometimes when an old workid matched in the queue it would trigger as a HW error, so better to not even receive useless nonces.

For klondike it doesn't send midstate back, only workid and each device in a chain has it's own sequence. I store (dev*256 + workid &0xFF) in the work->subid when sent and find it when a nonce comes back. I remove completed work when sending new work.

Quote from: fasmax on July 09, 2013, 06:45:15 AM

Quote from: BkkCoins on July 09, 2013, 06:35:25 AM

Just started running with 4 chips. 17 WU/m, 1200 GH/s.

Nice!
Are the 4 chips all on the same side or is it 2 and 2.

Right now just on one side, U5,6,7,8 at 300MHz. I have to relocate my NOR gate hack board before I can put chips on the other bank. U8 seems to run a bit hotter than the others at 52C. Others <50C. With steamboats black heat sink and a fan the heat sink runs 37C (on that corner, barely warm to touch) in 32 ambient.

fasmax

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Quote from: BkkCoins on July 09, 2013, 06:35:25 AM

Just started running with 4 chips. 17 WU/m, 1200 GH/s.

Nice!
Are the 4 chips all on the same side or is it 2 and 2.

kano

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Quote from: BkkCoins on July 09, 2013, 06:23:56 AM

Quote from: kano on July 09, 2013, 05:33:00 AM

If you want the number of HW errors like you are counting, it is simply the device HW - NMW
Avalon device HW is bad nonces + NMW

No need to change anything.

What/where is NMW?

That's an Avalon added stat
(No Matching Work)
If your version of the code isn't adding HW but just calling submit_nonce() with each one, then the HW counter will just be the number of submitted that were no good (and Diff1 Work will be the number submitted - that includes HW)

loshia

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Quote from: BkkCoins on July 09, 2013, 06:23:56 AM

Quote from: kano on July 09, 2013, 05:33:00 AM

If you want the number of HW errors like you are counting, it is simply the device HW - NMW
Avalon device HW is bad nonces + NMW

No need to change anything.

What/where is NMW?

NMW - No matching work count

joeventura

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Quote from: BkkCoins on July 09, 2013, 06:35:25 AM

Just started running with 4 chips. 17 WU/m, 1200 GH/s.

You are awesome!

Bicknellski

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Quote from: BkkCoins on July 09, 2013, 06:35:25 AM

Just started running with 4 chips. 17 WU/m, 1.2 GH/s.

Sweet.

BkkCoins

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Just started running with 4 chips. 17 WU/m, 1200 GH/s.

BkkCoins

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Quote from: freeworm on July 09, 2013, 05:06:51 AM

Your clock signal is great with very sharp rising/falling edge. I am wondering how you made it.
I simply added a NOR gate after the RC delay (100 ohm, 220pF) of your original circuit, but the signal is not as good as yours. The rising / falling time is much larger than yours and the pulses are broader.
It's better than the original circuit but I still get HWs.

The errors I get now are almost certainly on the input side rather than result capture, except the infrequent overrun I see get counted.

I use a trailing edge delay circuit. The first NOR gate has P and N, and it's output goes to A of 2nd NOR gate, then through a 100R resistor to B of 2nd gate. B has the 30pF to GND. So the 2nd NOR is ORing the clock with a delayed clock. The UART is set for rising edge capture, and data is inverted when read out of FIFO (~RCREG). This will be updated in the schematic very soon.

BkkCoins

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Quote from: kano on July 09, 2013, 05:33:00 AM

If you want the number of HW errors like you are counting, it is simply the device HW - NMW
Avalon device HW is bad nonces + NMW

No need to change anything.

What/where is NMW?

bigbeninlondon

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Quote from: turtle83 on July 09, 2013, 03:36:27 AM

Quote from: BkkCoins on July 09, 2013, 03:31:02 AM

Just got this nonce: b000bbbf Grin

close enough.
id like b000b1e5

Lol I love the professionalism.

kano

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Quote from: turtle83 on July 09, 2013, 03:36:27 AM

Quote from: BkkCoins on July 09, 2013, 03:31:02 AM

Just got this nonce: b000bbbf Grin

close enough.
id like b000b1e5

Line 899 of driver-modminer.c

kano

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Quote from: loshia on July 09, 2013, 04:17:04 AM

Quote from: BkkCoins on July 09, 2013, 04:08:20 AM

Maybe the ATX power is helping error rates. I'm getting 6 / 406 now, or about 1.5%. Much lower than last night on the wall wart, about 5%. Neither makes me happy but this is starting to get into a decent ball park.

Now tell me again how to calculate this properly using non 1-diff shares? I can't see a total count that includes difficulty accounted for. I know the git version now counts 1-diff shares, but is there a place to find that count on 3.3.1?

yes you can With little hack of course

...

The code already has those numbers ...

If the code passes a nonce to submit_nonce() it is counted in the device diff1
All nonces found by code go through submit_nonce() (including avalon)
The device diff1 is "Diff1 Work" which all devices already have.

If you want the number of HW errors like you are counting, it is simply the device HW - NMW
Avalon device HW is bad nonces + NMW

No need to change anything.

Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 74. (Read 435369 times)