Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 75. (Read 435369 times)

Your clock signal is great with very sharp rising/falling edge. I am wondering how you made it.
I simply added a NOR gate after the RC delay (100 ohm, 220pF) of your original circuit, but the signal is not as good as yours. The rising / falling time is much larger than yours and the pulses are broader.
It's better than the original circuit but I still get HWs.

yes you can With little hack of course

Here is the magic:
Driver avalon.c near line 736
if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
   mutex_lock(&info->lock);
  if (!info->nonces++)
  gettemp = true;
  info->auto_nonces++;
  info->auto_totnonces++;
  mutex_unlock(&info->lock);
} else if (opt_avalon_auto) {
  mutex_lock(&info->lock);
  info->auto_hw++;
 info->totauto_hw++;
  mutex_unlock(&info->lock);
} else {
mutex_lock(&info->lock);
  info->totauto_hw++;
  mutex_unlock(&info->lock);
}

Define  info->auto_totnonces and   info->totauto_hw in driver avalon.h both int

Init/zero them somewhere in avalon_detect_one just to make it pretty
and finally around line 1285

root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);

Add
root = api_add_int(root, "totauto_hw", &(info->totauto_hw), false);
root = api_add_int(root, "auto_totnonces", &(info->auto_totnonces), false);

That is how i do that for the avalon and it works  
And i can calculate good nonces per sec also ...and other fancy stuff
What i can tell that Con auto-freq code works rock solid and keeps hw% below 2% as advertised

Maybe the ATX power is helping error rates. I'm getting 6 / 406 now, or about 1.5%. Much lower than last night on the wall wart, about 5%. Neither makes me happy but this is starting to get into a decent ball park.

Now tell me again how to calculate this properly using non 1-diff shares? I can't see a total count that includes difficulty accounted for. I know the git version now counts 1-diff shares, but is there a place to find that count on 3.3.1?

close enough.
id like b000b1e5

lol

b000b13s would be even better

Just got this nonce: b000bbbf  

+1 On that. A way to make sure all 16 chips hashing OK is a must. Otherwise it may turn that only I/O works and to loose hashing power

Probably active cooling but it seems like not that much airflow is needed so it could be very quiet. I'm just guessing right now based on how the first 3 chips are heating up. A big heat sink may be enough. I've run two chips fine with no cooling. Then I added a fan and the chips stay really cool. So then added a third and the heat sink doesn't even get warm with a fan. We'll see when the full 16 chips are putting energy into the heat sink, and for sure I'll report it here.

I also switched from 12V adapter to my ATX supply now. I hoped it would improve error rates due to better power but made no diff. Just prepping for adding up to the full 16 chips now. The wall wart couldn't handle more than 3-4.

BTW I've also been revising the PCB now as I want to get new ones made ASAP. I'ved changed the NOR gate to Dual NOR Gate, added a Schmitt buffer that could be easily left off by jumping it if not needed, and will add 16 ferrite beads to try improve the PLL stability.

This code could actually be useful for detecting if chips are fully functional (each nonce range) if it could report a distribution of nonce values, 0 -> 2^32. Right now, I eye ball the nonce results and check if they seem to cover all values without duplicates (overlap). Maybe I should add an range accumulator into the nonce check to verify each chip is doing what it should be.

just a small question:

the not overclocked K16, will it need active cooling (fan) or is a heatsink enough?

And yes it's in the API 'stats' of course.

Thanks.  Building now.

My git https://github.com/kanoi/cgminer
I'm not committing code in the master git at the moment while contact with ckolivas is sporadic - he's on holidays

anyone have a idea/link of a good dc fan to mount on the heatsink for oc

what would be the max fan dimensions of the fan to fit , if I intend to stack K-16 on top of another ?

It looks like the Avalon design used a 20 amp regulator. This gives 2 amps per chip. The k16 also provides 2 amps per ASIC.
So if people are over clocking their Avalon design then I would think the K16 regulator would allow similar over clocking.

Here's some info I posted a while back in a PM.


Note that the reg has over current shutdown minimum 18A and the inductors are rated for 18A (which is when it's temp rises 40C above ambient).

I think each chip is 2W.  I'd imagine they'd be the bulk of the power use, maybe 80%?  (I just made that % up)

I know somewhere in this thread is the estimated wattage / amperage for each board. What was it @ 256MHz? what is it / to be expected at 350MHz? JUst trying to plan out the most cost effective PSU for amps on the 12v rail and wattage

Kano, is there somewhere we can checkout the modified cgminer with the bflsc nonce stats?  I'd love to go further down the rabbit hole on these nonce statistics using a Jalapeno.

Thanks.

Those results look very close the theoretical values for the relevant Poisson distribution (lambda = 1). The first 11 theoretical values are: {367.88, 367.88, 183.94, 61.313, 15.328, 3.0657, 0.51094, 0.072992, 0.009124, 0.001014, 0.000101}. This makes sense, since mining is a Poisson process.

Something I learned: multiple nonces within one work unit occurs about 2/3 as often as a single nonce. So you should be prepared to handle multiple nonces.

I've made up plenty solderless breadboard prototypes using a 20MHz crystal for a PIC and have managed to not knock out my cell reception.  I'm sure it'll be fine.