As i stated above i personnaly keep pursuing this idea since i started the thread.
But it seems im the only one working on this right now beside my job so its extremly slow.
If anyone wishes to help push this concept on, she or he is very welcome.
Topic: Modular FPGA Miner Hardware Design Development (Read 119276 times)
I like this idea. Is the project still alive?
I might try on one of my solder/Power supply/stability testboards since it seems i wont need them for now.
I will runn some Tests an report in case i cook them
If the competing approaches reall reach markt as promised this development might be obsolete since this developing thread seems down to me alone.
I cant keep the pace.
So we will see.
I will runn some Tests an report in case i cook them
If the competing approaches reall reach markt as promised this development might be obsolete since this developing thread seems down to me alone.
I cant keep the pace.
So we will see.
No i haven't tested it at that core voltage yet.
I asume this would also considerably shorten the life span.
I asume this would also considerably shorten the life span.
But, by how much? Assuming proper cooling, the rated max for VccInt is 1.32. Above 1.25 may not leave enough room for spikes on power down, but shouldn't raise operational temp all that much. If I ever get any of the things here I will test some out on extended runs.
No i haven't tested it at that core voltage yet.
I asume this would also considerably shorten the life span.
I asume this would also considerably shorten the life span.
Has anyone tested the -3 grade at 1.27v or above for error rate, etc?
IMO the upper limit for 6s150 -3 is around 200MH/s w/o overclocking.
ArtForz was claiming ~193MH/s with his design; closest I've gotten is ~156MH/s.
And getting that to build through ISE was quite a challenge.
If you can reach 250M/s in -2, you are probably one of the top 10 FPGA designers in the world
and should be working for the finance sector or govt/military instead of wasting time on bitcoin.
-rph
ArtForz was claiming ~193MH/s with his design; closest I've gotten is ~156MH/s.
And getting that to build through ISE was quite a challenge.
If you can reach 250M/s in -2, you are probably one of the top 10 FPGA designers in the world
and should be working for the finance sector or govt/military instead of wasting time on bitcoin.
-rph
yeah, I think so.
IMO the upper limit for 6s150 -3 is around 200MH/s w/o overclocking.
ArtForz was claiming ~193MH/s with his design; closest I've gotten is ~156MH/s.
And getting that to build through ISE was quite a challenge.
If you can reach 250M/s in -2, you are probably one of the top 10 FPGA designers in the world
and should be working for the finance sector or govt/military instead of wasting time on bitcoin.
-rph
ArtForz was claiming ~193MH/s with his design; closest I've gotten is ~156MH/s.
And getting that to build through ISE was quite a challenge.
If you can reach 250M/s in -2, you are probably one of the top 10 FPGA designers in the world
and should be working for the finance sector or govt/military instead of wasting time on bitcoin.
-rph
Hi guys. What's up with this development? Nothing has happened in a few weeks, is it dead?
ngzhang: Your miner board is very interesting! Do you have any real-world performance data? Is the board stable? What's the current consumption on the FPGAs? I'm looking forward to the schematics and other files on that board.
ngzhang: Your miner board is very interesting! Do you have any real-world performance data? Is the board stable? What's the current consumption on the FPGAs? I'm looking forward to the schematics and other files on that board.
These days, I fixed some bugs on the hardware and relayout the PCB. Another 10 boards are under manufacturing. Coming out soon.
On the firmware side:
With a single FPGA running LX150_makomk_Test's code, a speed of 120MH/s perFPGA has been reached. looks very stable. We only use a -2 device.
with ourselves' UART communication mining code, a test version could mining @ 50MH/s and not very stable, maybe there are some P&R problems. Because lack of time, we just checked the function, it works.
Now we are testing the the FPGA mining chain, this part is still under coding.
The mining core is the most important part of this project, so after finish the mining chain architecture, we will put 100% efforts on this core.
Correct makomk's core use SLR16s to save resources, but this cause a terrible P&R difficulty. But if don't use the SLR_16s, there are not enough registers. Solve this conflict will lead a single FPGA to 250MH/s at least.
Well, I have to say that I have had my own FPGA cluster under development for some time. I originally designed it for hash breaking (such as MD5) but why not Bitcoin mining as well. The specification is quite a bit different than what has been proposed here. My design has one baseboard with an Atmel AVR USB-enabled microcontroller that handles all host communication and FPGAs communicate via I2C. The baseboard provides a JTAG chain and a 5V/5A power supply. If some slack conditions are met (i.e. I2C and JTAG voltage levels) then the system is completely agnostic to what is doing the actual processing. The mechanical layout is copied from Arduino, so that modules simply stack on top of each other.
Currently I am in the process of laying out the baseboard and after that I will probably do a simple Spartan-3E QFP processing unit. Sure, S3E sucks at mining BTC hashes but it's a start and you can later on develop more sophisticated units like S6LX150.
Summa summarum: I am hesitant to help with design that I disagree with (the design discussed in this thread). That and I know absolutely nothing about the TI MSP430. But I'll keep watching this space...
Currently I am in the process of laying out the baseboard and after that I will probably do a simple Spartan-3E QFP processing unit. Sure, S3E sucks at mining BTC hashes but it's a start and you can later on develop more sophisticated units like S6LX150.
Summa summarum: I am hesitant to help with design that I disagree with (the design discussed in this thread). That and I know absolutely nothing about the TI MSP430. But I'll keep watching this space...
Hi,
Basically its still up and running. But as i see it, the crew has reduced itself to me alone.
And im struggeling to programm the MSP (still learning on microcontroller programming).
So the advance is minimal but present.Therefore any help is appreciated.
Basically its still up and running. But as i see it, the crew has reduced itself to me alone.
And im struggeling to programm the MSP (still learning on microcontroller programming).
So the advance is minimal but present.Therefore any help is appreciated.
Hi guys. What's up with this development? Nothing has happened in a few weeks, is it dead?
ngzhang: Your miner board is very interesting! Do you have any real-world performance data? Is the board stable? What's the current consumption on the FPGAs? I'm looking forward to the schematics and other files on that board.
ngzhang: Your miner board is very interesting! Do you have any real-world performance data? Is the board stable? What's the current consumption on the FPGAs? I'm looking forward to the schematics and other files on that board.
usually, high speed signal are organized in differential pairs, and these pair groups are in (approx.) same length. So "squiggly traces" is a method to guarantee the length.
You can find them in most high speed designs, maybe on your motherboard or GPU cards.
I take it each of those pairs of lines is connected to an associated pair of differential pins on one of the FPGAs then? That sounds like it could make the boards rather more versatile.You can find them in most high speed designs, maybe on your motherboard or GPU cards.
Certainly. The DIMM has 22 pairs on each FPGA. (44 total) And another 10 pairs each FPGA on the top.(20 total, using a tyco connector).
also 8LEDs and 8 DIP switchs.
usually, high speed signal are organized in differential pairs, and these pair groups are in (approx.) same length. So "squiggly traces" is a method to guarantee the length.
You can find them in most high speed designs, maybe on your motherboard or GPU cards.
I take it each of those pairs of lines is connected to an associated pair of differential pins on one of the FPGAs then? That sounds like it could make the boards rather more versatile. You can find them in most high speed designs, maybe on your motherboard or GPU cards.
What's up with those squiggly traces, ngzhang? Never seen that before
usually, high speed signal are organized in differential pairs, and these pair groups are in (approx.) same length. So "squiggly traces" is a method to guarantee the length.
You can find them in most high speed designs, maybe on your motherboard or GPU cards.
What's up with those squiggly traces, ngzhang? Never seen that before
Usually, those are used to equalize the lengths of lines used for high speed busses. Unequal lengths = unequal delays. Unequal delays =
What's up with those squiggly traces, ngzhang? Never seen that before
Hi ngzhang
I would even prefere information about your current " buggy" version over waiting for some weeks.
As you will be aware we in this thread are highly in need for some feedback and second views onto the hardware side.
So i would appreciate it if you could give us some more details.
I would even prefere information about your current " buggy" version over waiting for some weeks.
As you will be aware we in this thread are highly in need for some feedback and second views onto the hardware side.
So i would appreciate it if you could give us some more details.
Here is the final structure chart.
You know there are competitors. So the detail schematics WILL release a few weeks later.
Hi ngzhang
I would even prefere information about your current " buggy" version over waiting for some weeks.
As you will be aware we in this thread are highly in need for some feedback and second views onto the hardware side.
So i would appreciate it if you could give us some more details.
I would even prefere information about your current " buggy" version over waiting for some weeks.
As you will be aware we in this thread are highly in need for some feedback and second views onto the hardware side.
So i would appreciate it if you could give us some more details.
Nice to see you making such huge progress ngzhang.
Seems your outrunning us in development.
How do you intend to go on with this board ?
Will you share some details or is it not to be published or inbound to our project ?
Seems your outrunning us in development.
How do you intend to go on with this board ?
Will you share some details or is it not to be published or inbound to our project ?
There are full of bugs on this board. now. But it could work and mining @ 100MHs/each FPGA based on Mokamk's code.
I'm thinking over is or isn't to keep the DIMM golden finger. It really make a high cost on PCB manufacture(50%+ cost). And some other electrical modifications are needed. All these things will be done in 2 weeks, and we will see the 2nd generation.
On the other side, our mining code on it is still under development, maybe release in 2 weeks. It will be like to reach a higher performance.
After these work , BEFORE commercial release of this board, all schematic of this board and mining code of standard performance will post on this forum.
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