Topic: Modular FPGA Miner Hardware Design Development - page 4. (Read 119320 times)

film2240, I think you missed some of the details of this design. I know that there's a lot of information in 30 pages of this thread and it can be hard to digest it all quickly. O_Shovah's first post does a good job to summarize the current state, but I'll reiterate some of it here and add to it a little bit.

We are designing a two FPGA board. The interface between the FPGAs and the outside world will be through a small microcontroller. The MCU will connect directly through a USB port on the board, or down to a bus on a "motherboard" through the DIMM connector. The idea is that these FPGA boards can be operated as a small USB device or as a module riding in a larger array of these boards, a la this. The motherboard in this case is yet to be designed (it isn't a standard PC motherboard), but it is planned to have power distribution, bus connections, and a USB port in the first iteration. Later, we have discussed adding an ethernet interface that will connect directly to the internet, without a host computer.

There are three ways to get power to the board:

• through a 4 pin Molex connector from a standard computer PSU
• through a barrel connector from something like a laptop AC adapter
• through the DIMM connector coming from the motherboard

The key here is modularity and flexibility. This means you can buy as many or as few boards as you like, and set them up in whatever way you like. It also means that the basic design can be modified but different designs can coexist in the same system, as long as the all follow the same communication protocols. Furthermore, the boards can be reprogrammed, so can easily adapt to future design changes.

This is hte 1st time I've ever contributed to FPGA miner dev posts so I don't know much about FPGAS/DEV stuff.I have many suggestions.

If we are to follow the conventional way of doing things (each board has it's own processsor,I/O,power lead et.c),I think it's essential to reduce the no of needed parts to reduce costs.
1.Instead of the need to add additional power connectors,why not just make each board a PCI-E x4 or PCI-E x8 depending on the power needed rather than simply adding several power connectors.This way we can eliminate the need for a mains lead/PSU (could save $20 off build) as well as the space dedicated to having several possible PSU connectors.This is ok for FPGA boards that are meant to be added into a PC and then programmed easily with a GUI Utility (which relates to my preference for easy flashing/running of binaries of need be).
2.To tackle the issue of I/O,I think to save costs again we simply remove the need for storage connector and replace with a suitable sized flash chip that is soldered straight onto the board,that way we can save PCB space (from where the storage connector used to be) and possible save costs/make it more convenient for us users.
3.Again I do think that all RAM should simply be soldered directly to the board,eliminating the SDIMM sockets thus saving space on the PCB and reducing bill of materials a little.

I think this will work for people like me who wish to have a premade/pre configured board with an internet connection (preferably sharing my PC's ethernet without requiring a seprate port for each FPGA board.

I do wish to see the ultimate board of a FPGA,where it's like several FPGS chips sharing 1 set of I/O,solely powered by PCI-E x8 slots (as the extra lanes provide up to 75Ws on PCI-E v1 spec mobos.),have a 2 position switch,1 stock and 1 max performance like on the Radeon HD6990.

I mainly have ideas for boards that run from the PC and that are not independant.

yep, assembling BGAs is a problem @ earth. In China, it's about 0.5CNY/pin。a 484 BGA cost a soldering fee for  242CNY(38$).
Also, DIY soldering a 484 BGA is an impossible mission.

Awesome thread and project.

How are you guys planning to assemble it when it's done?
Here in the US, low-vol BGA assembly is very expensive,
unless you can DIY. And that takes some guts w/ 2 $160 FPGAs.

-rph

Hi O_Shovah,

You're right, it's especially quiet around here lately...

I already added a few LEDs to the schematic. There is one on VUSB to indicate that USB power is present, and 4 on general purpose pins that can be used to indicate anything we want from the MCU firmware. We can certainly add more (as many as we have free pins). Another thing I wanted to add was some temperature monitoring. I think some thermistors placed on the board near the the FPGAs would work. Does anyone else have other ideas for this?

Tanks fizzist

I ll also check on the new schematic just to be shure.

I will try to add the debugging leds later two. Should be as easy as to asign one output top led and ground or am is mistaken ?


Also maybe for the rest of our fellow developers li_gangyi and OlafMandel.
Are you currently busy with other things to do, or do i just imagine haven't seen you around for some time now ?
Please just give a small sign of live.         

Updated the MCU schematic in my folder on Dropbox. Changes:

1) Added part for MSP430F552x to project.lbr (copied from official TI library).

2) Replaced MSP430F5507 with 'F552x in the PN80 (aka QFP80) package. This was a big job, so I still need to go through and double check everything for any mistakes.

Yes it seems i misunderstood you. I just thought you proposed to change our current setup according to your schematic.

But running our two developments in paralel shurly will bring benefits for both of us.I appreciate that.  

Regarding IOs, I didnt mean that we are close to running out, only trying to come up with an idea for how many we need. Actually, all the 55xx series have more than 30, I believe.

I agree that it makes sense to just go with the beefiest MCU for now, at least. It will give us the most flexibility for the prototype. If we see that it's extreme overkill, we can downgrade for the first production model. I'll find some time later to switch to the 5529 in the schematic.

There must be some misunderstanding.
Our purpose is slightly different here. The works of yours is facing directly to a simplest platform for FPGAmining, easily to development. But I am a Ph.D candidate, majored in high performance computing, so in my concept, go a little bit further  for universal use, and cost reduction.
But there are still most of the important parts keep alike. So I think we could push each project forward in the meantime, share each problems and discovers, and discuss them.

It is a great pleasure for me to discuss with you.
For not disturbing this thread, I'll update my design in #579.

Ok so to improve the todo list:(EDIT)

- completing MSP 430 integration (fizzist claims that we might run out of IO in case we use debugging leds. I personally would vote for the 5529 MSP as it provides maximum performance without high price raises)  

- clarify if the 0402's are nessecary ( i personally would use them to stick to the specification as close as possible)

- intergration of debugging devices ( pin headers, leds ,peepers) ?

- completing routing on the DIMM

-Decide if we should switch from the LMZ12010 to the smaller and cheaper LMZ12002 (or 3) for the 2.5V rail. (i personally would leave the current setup widely untouched.
 We may meassure the real current while testing and may choose a DC DC converter acording to that for the series)

- resistors in the power supply ?

- Decide on cooling method. These could mean leaving mounting holes (or clearance for the Radian EZ-Clip) and fan headers.


So who is going to aim for wich task please ?


@ ngzhang:

No personal offence, but your global setup highly differs from the one we decided on(Power supply, USB, Bus, routing). Turning to this one now would throw us back to stoneage.

every xc6slx150 need about 33.9Mbit for config. 2 if them could use 1 flash to store 2 config bitsteam in it. about 68Mbit. use a m25p128 to do it. about 20CNY (2€)1 pcs here.



EDIT


EDIT2？

Why no QFNs?

Hand soldering this board is IMPOSSIBLE. Because soldering the 484pin BGAs need BGA rework station or reflow-soldering system. They also can soldering QFNs very easily.

I'm thinking about the MCU decision again. I'd like to summarize the discussion on this so far.

Package: li_gangyi would prefer to stay away from QFN. As long as there is a non-QFN choice, and we aren't pressed for space, I don't see any reason to go with QFN.

IOs: The current schematic has 15 digital IOs used. We will also need a few debugging LEDs, say 4. I think we also need a couple of analog lines for temperature monitoring. Let's say 30 is the minimum number of IOs.

Flash memory: We still have no good estimate for this. I would guess 32 kB is the bare minimum, and the more the merrier.

Based on those points, we are limited to the following parts (notes are flash+SRAM, price):

MSP430F5510 (32+6kB, Non-stock at Digikey)
MSP430F5521 (32+8kB, $7.30)
MSP430F5525 (64+6kB, $8.06)
MSP430F5527 (96+8kB, $8.52)
MSP430F5529 (128+10kB, $8.73)

Based on that, we only really need to decide on the amount of program space needed. Does anyone have a guess?

Yes, partly you are right. In large quantity, they use wave-soldering(for through-hole comps.) and reflow-soldering(for SMT comps.).
But in low quantity, they use man hand to soldering through-hole comps and discrete comps, use a BGA rework station to soldering BGAs and QFNs. Because the wave-soldering and reflow-soldering cost a huge prepare time. So they start at a minimum fees(maybe 50,000 CNY of soldering fees here).

So, we may have to soldering with a few boards, the cost is depend on the pin-count on the board. Here they are about 0.05 CNY/ pin. And the BGAs are expensive, plus a 0.5CNY/BGApin. Of course, you can cut down some fees when you are soldering 100 boards on time, it's a mid-quantity for some small factory.

PS:
I strongly recommend use through-hole electrolytic capacitors and headers instead of SMTs . Because man hand soldering CAN NOT soldering large SMT comps well. They may easily to drop off.

EDIT:

ok, now I didn't go to school(I'm now a phd student ) and worked on this project for 1 day.
I think, if we want to push this project a little faster, may be we must confirm some thing. 1st is a fixed interface of the daughter board.  I think, #508 's design maybe wasted too much gold-finger pins. We can made the daughter board to be used more universally, such as a Accelerate Unit in high performance computing, fit with other computing project, but no addition costs. I'm working on it and will release it tomorrow. I hope finish it in 1-2weeks and got a example at the beginning of Sep.


EDIT2:
Design concept. UPDATE 2011/8/16



The DIMM socket must have 5V and 12V supply, but the daughter board could select to use 1 of them or both of them, for the maximum  compatibility. In correct design, Only 512V is used.

EDIT3:
Add: FPGA JTAG chain and config circuit.


NOTE that FPGA1_SCK signal also connected to FPGA2 CCLK pin. FPGA1's DOUT pin connedted to FPGA2 CSI_B pin.

Really?  I figured they would just use a wave machine or a reflow oven.

I've designed several PCBs, and sent them out for low volume fabrication before, but I've never had one assembled, or really even looked into it.  I just sorta assumed that it was pay per board, or pay per unit area.

I like that elliptical fin heatsink. As for the idea of one big heatsink, the Radian HS1594EB might work. It's similar in size to the one you linked to, but has mounting screws and the fins are oriented in the correct direction (parallel to the longer dimension). I drew an outline of it over Olaf's FPGA section, to get a sense of the size:



If we make sure to put those holes in the board and keep any tall components out of that area (greater than 2 mm), we'll have the flexibility to use either of these two options.

Errrrrrrrrrrrrr...

I read through this thread, I apologize but the feeling is not good. This project is lack of professional guys to do it.
In my opinion, the daughter board and mother board could develop independently, the daughter board have one 5V  input jack, and a USB to UART bridge, in order to connect to a PC and run standalone. and the DIMM connector is a good idea, but please, please use DDR2 - 184PIN socket instead of DDR3- 240PIN socket. Because the soldering fees is depend on the pin count. Then, let "some" GPIOs of the fpga to the connector is enough.

Power the fpgas is very important, use a DC-DC switch to provide about 15A　VCCINT for the 2 XC6SLX150 -3N s will be enough.

and that is all, maybe 3~5days work for an Experienced engineer.

OK ,lets talk about the cost. Now in my country, a XC6SLX150 is about 1000CNY. sampling a 4 layrs PCB ( in acceptable quality), is about 1000 CNY/ time. and maybe 10-20CNY each.  The DC-DC switch circuit is about 50CNY of BOM cost. soldering fees is very high in low quantity, about 200CNY/ PCB. and something others.

so if we build 20 of them, we need:

40FPGAs : 40,000 CNY
PCB: 1,000 CNY
soldering: 4,000 CNY
all other things on the PCB: 4,000CNY(MAX)

less than 50,000 CNY, we got 20 of them. 2,500CNY  each.

If the fpga coding team works well, 200Mh/s of each chip, we got 4Gh/s with 50,000 CNY. The power is about 200w.

50,000 CNY = 7,700 US$

For 4Gh/s, we must use 15 HD6870s in STD FREQ, this cost about 30,000 CNY here(Include PSUs, mother boards, etc. ). These GPUs consuming 3KW of power.

I'm very very sorry about my language. If there are any misstanding, please point out and I will explain it on my best effort.

Thank you.

Independent verification is always a good thing! Especially when I did the calculation!

Thanks! I just now finished the same calculation and got the same results (didn't check the forum first)   

Just looked back a couple of pages, and TheSeven actually suggested 1.25V, because 1.26 is the max allowed. For that, R_FBT = 1.07k and R_FBB=1.87k gives 1.24989V.

Also, the question of resistor tolerance came up a while back. With this combination and 1% resistors, the worst cases give 1.2591 and 1.2409, which I think is sufficient.

I made the change to the schematic in your folder, and updated the BOM database with those resistor values.