Hi giorgiomassa
Nice to hear from you again.
And it is great to hear, that you did some serious progress.
Actually you posted today more in your official thread than in the past four weeks (sorry for this one, but just could not resist
)
There's just a few things I would like to clarify.
I assume most of your customers were somekind of expecting a delay - especially the ones who have done some engineering projects themselves
You just can say how much time it takes to find proper solutions to all the nuts to crack and after once you're finished with you first draft one can just guess on how long the bugfixing period will be.
However:
Everybody in the EE industry knows how long it takes to manufacture 4 layers board prototype, have them assembled and do research and measures on each board revision to find issues
this is exactly the point that bothers me here. Once you communicated the three week delay on Dec. 10
th or at least with you first samples you picked up on Dec 31
st you must have known, that a three week delay will most probably not gonna happen.
So I would highly appreciate If the official communication of bitmite with their customers would be more frequent and more transparent.
Sure it would not have been nice to hear that after the second try also the third PCB still has some flaws, but without any news, we don't even know wether the chips won't explode after 15minutes of hashing
So even if you are afraid of posting "bad" news which might make some users nervous, I think you would be suprised on how much support you would get in this forum If you would communicate more openly. Most of your customers are not dissapointed because of the delay but the way the communication works at the moment.
Which brings me to the next topic.
Obviously you are still debugging the PCB(s) (since I assume there will be different ones for Desks and Rigs).
Based on your post here:
Remember that these are from a pilot run of the IC packaging, our guys in China have done several further optimizations in the meantime like the glue and the wires used inside the IC, also we did tweak some parameters with the foundry for future wafers, so the chips are going to be definitely much better in production run (coming probably next week already) than these samples.
you were also improving the A1 chips themselves. Did you already revieve some samples of the new version? If yes, did they bring the expected improvements?
And the third hardware related question would be the Turbo mode. To my understanding after some weekend and overnight work (a big thank to your Engineering team this point) you managed to get up to 10 chained A1 chips to operate in a way where they scale (almost) linear. However based on this experience and the findings posted in the thread mentioned above it looks like the turbo mode might be an issue. Did you already try to operate these Babys in turbo mode or was this not possible yet due to the flaws in the sample chips and PCB(s)?
If I combine these two main topics, I would like to propose the following.
Consider to make a sort of list with all the main topics which you need to resolve in order to start with assembly/production on your end and provide an update on this list twice or three times a week in this thread. This could for example look like the following:
to all users: I just made up these points to visualize my proposal, so don't take this as any kind of truth - and don't start flood this thread with posts calling this FUDing, since it is just an example!- [OPEN] resolve parasitic interferences on the PCB created by the high switching currents of the DCDC. A more radical re-routing of the board layout has been performed these last days and we're awaiting the fourth generation of the PCB(s) for mid this week.
- [OPEN] the heat dissipation of the chips needs to be improved. The packaging process (glue & wiring) has been improved. New samples have arrived today and are currently under assessment. results will be posted by mid week.
- [OPEN] verify that the boards&chips can be operated stable in turbo mode for at least 48hours. waiting for final PCB Version (see above)
- [OPEN] place the order for bulk PCB production. waiting for all open PCB issues to be closed. Once ordered we recieve the first PCBs after 4 working days with a capacity of about 250PCBs per day
- [OPEN] place the order for bulk chip production & packaging. waiting for heat dissipation assessment of new packaging version. Once ordered we recieve the first fully packaged chips after 8 working days (3 days chip production, 5 days packaging) with a capacity of about 3k chips per day
- [CLOSED] get the chips to work in chains longer than two chips. Introducing a clock divider in PCB rev 2 resolved the problem
- [CLOSED] recieve first sample chips from packaging facility.
to all users: I just made up these points to visualize my proposal, so don't take this as any kind of truth - and don't start flood this thread with posts calling this FUDing, since it is just an example!Would this be an idea worth taking up?
regards