Dear disciples of the Open source FPGA,
I need your insght. I posted my question in ZTEX's BTC Miner thread, but it is really more of an open source question. I just posted there because it is a more active thread.
Please see my post on this page and if you can help me on the ZTEX Open Source Build procdure please do!
https://bitcointalksearch.org/topic/m.1087521
Thank-you.
Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 21. (Read 432950 times)
August 09, 2012, 08:14:34 PM
April 11, 2012, 03:00:37 PM
Just try it, look what performance numbers you get and if it gives some improvement the community will drooling after it.
As far i know the hasher has to be constructed a special way so ISE can produce an efficient bitstream from it, so it could be necessary to modify the ztex core for different hasher pipe length.
Maybe the speed decreses with a higher Slice count due to routing problems, but maybe it works ...
As far i know the hasher has to be constructed a special way so ISE can produce an efficient bitstream from it, so it could be necessary to modify the ztex core for different hasher pipe length.
Maybe the speed decreses with a higher Slice count due to routing problems, but maybe it works ...
April 11, 2012, 01:59:50 PM
i did some calculations in the last weeks about multicore on LX150
so a ztex-hasher + an LOOP2-hasher would fit in one LX150, i tried working out something but i didn't do FPGA-coding before
any opinion on this?
so a ztex-hasher + an LOOP2-hasher would fit in one LX150, i tried working out something but i didn't do FPGA-coding before
any opinion on this?
March 12, 2012, 07:44:20 PM
I'm very glad I found this project! I am EE hobbyist and my recent focus has been FPGAs.
Quick question; has anyone implemented this on a Xilinx Spartan-3E 1200K? I know it has been done with the Spartan-3E 500K (the cheaper Nexys2 board), but I haven't seen it so far with the more expensive board. If no one has done it yet, I'll get on it when I have some free time.
Quick question; has anyone implemented this on a Xilinx Spartan-3E 1200K? I know it has been done with the Spartan-3E 500K (the cheaper Nexys2 board), but I haven't seen it so far with the more expensive board. If no one has done it yet, I'll get on it when I have some free time.
March 01, 2012, 03:52:42 PM
made small alteration to the tcl script for mining. I altered wait for golden ticket adding a small delay. This will delay seemingly the found nonce by an amount of time but I am still sitting at a little abov 6Mhash/S. I am unsure if the delay will free up FPGA time or not. The 50ms delay will still check around 20 times a second and system load dropped significantly. Here is what I did.
Code:
while {$timeout > 0} {
set golden_nonce [get_result_from_fpga]
if {$golden_nonce != -1} {
return $golden_nonce
}
# TODO: We may need to sleep for a small amount of time to avoid taxing the CPU
# Or the JTAG comms might throttle back our CPU usage anyway.
# If the FPGA had a proper results queue we could just sleep for a second, but
# for now we might as well loop as fast as possible
set now [clock clicks -milliseconds]
if { [expr {$now - $begin_time}] >= 2000 } {
incr timeout -2
set current_nonce [get_current_fpga_nonce]
set dt [expr {$now - $begin_time}]
set begin_time $now
if {$current_nonce < $last_nonce} {
set nonces [expr {$current_nonce + (0xFFFFFFFF - $last_nonce) + 1}]
} else {
set nonces [expr {$current_nonce - $last_nonce + 1}]
}
set last_nonce $current_nonce
if {$dt == 0} {
set dt 1
}
set rate [expr {$nonces / ($dt * 1000.0)}]
set current_time [clock seconds]
# Adding 0.00001 to the denom is a quick way to avoid divide by zero :P
# Each share is worth ~(2^32 / 1,000,000) MH/s
set est_rate [expr {($total_accepted + $total_rejected) * 4294.967296 / ($current_time - $global_start_time + 0.00001)}]
say_status $rate $est_rate $total_accepted $total_rejected
}
#Added a delay of 50 MS between checks of FPGA for a Golden Nonce.
#if script fails is likely here
after 50
}
Delay is at the bottom but I wanted to show where to put the delay if one wants it delayed only before the next check. It does change the printout from every 2 seconds to a little more then 2. Every 10 seconds or so I get a single 3 second space. Likely the exact after number could be adjusted to keep it to only 2 seconds. set golden_nonce [get_result_from_fpga]
if {$golden_nonce != -1} {
return $golden_nonce
}
# TODO: We may need to sleep for a small amount of time to avoid taxing the CPU
# Or the JTAG comms might throttle back our CPU usage anyway.
# If the FPGA had a proper results queue we could just sleep for a second, but
# for now we might as well loop as fast as possible
set now [clock clicks -milliseconds]
if { [expr {$now - $begin_time}] >= 2000 } {
incr timeout -2
set current_nonce [get_current_fpga_nonce]
set dt [expr {$now - $begin_time}]
set begin_time $now
if {$current_nonce < $last_nonce} {
set nonces [expr {$current_nonce + (0xFFFFFFFF - $last_nonce) + 1}]
} else {
set nonces [expr {$current_nonce - $last_nonce + 1}]
}
set last_nonce $current_nonce
if {$dt == 0} {
set dt 1
}
set rate [expr {$nonces / ($dt * 1000.0)}]
set current_time [clock seconds]
# Adding 0.00001 to the denom is a quick way to avoid divide by zero :P
# Each share is worth ~(2^32 / 1,000,000) MH/s
set est_rate [expr {($total_accepted + $total_rejected) * 4294.967296 / ($current_time - $global_start_time + 0.00001)}]
say_status $rate $est_rate $total_accepted $total_rejected
}
#Added a delay of 50 MS between checks of FPGA for a Golden Nonce.
#if script fails is likely here
after 50
}
February 28, 2012, 09:22:06 AM
watching
February 25, 2012, 05:04:41 AM
i got 3 board with 11x xc95108
datasheet says one xc95108 has "108 macrocells with 2,400 usable gates"
i don't know if "2,4k per macrocell" or "2,4k all together"
datasheet says one xc95108 has "108 macrocells with 2,400 usable gates"
i don't know if "2,4k per macrocell" or "2,4k all together"
I would bet the 2.4 kGates equivalent is for the whole chip. Well, this CPLD has 108 register, that means it can store 108 bit of Information, but for one round you need 512 Bit for storing the information ... maybe you could implement a single stage Hasher that would need 64 rounds using all chips, but performance will be very poor.
February 25, 2012, 04:05:23 AM
i got 3 board with 11x xc95108
datasheet says one xc95108 has "108 macrocells with 2,400 usable gates"
i don't know if "2,4k per macrocell" or "2,4k all together"
datasheet says one xc95108 has "108 macrocells with 2,400 usable gates"
i don't know if "2,4k per macrocell" or "2,4k all together"
February 25, 2012, 04:00:00 AM
Sure, if you find a CPLD that is big enough to fit a hasher in it ... in fact there have been FPGA with classic sum of products type elements on it, but seems there were no benefit from this.
February 25, 2012, 03:32:42 AM
are there some reasons we can't run this on CPLD?
February 24, 2012, 05:35:43 PM
Hello, i have a EP2C35 board with an adapted version of the DE2_115_makomk_serial design, with CONFIG_LOG_LOOP2 set to 1 and 60 MHz Clock rate. This should give me 30 MHash/s, but i only get poor results. I use the the script in the project directory as well a the original Script be tecknohog and the scripts tell me wildly varying results, which should be ok but runnig for several hours, the result is very poor. There are no error reports because of wrong results.
The FPGA has a small heatsink on it, but keeps in the 30-40 Degree Celsius range.
Since the serial connection works, i think the PLL gives the correct clock, ...
Could the error due to a under dimesioned Power supply or insufficient decoupling? The board has an switching regulator rated @ 6 or 8 A, but i don't know if the power inductor or another piese of the board could cause this
Any ideas?
The FPGA has a small heatsink on it, but keeps in the 30-40 Degree Celsius range.
Since the serial connection works, i think the PLL gives the correct clock, ...
Could the error due to a under dimesioned Power supply or insufficient decoupling? The board has an switching regulator rated @ 6 or 8 A, but i don't know if the power inductor or another piese of the board could cause this
Any ideas?
February 19, 2012, 11:20:59 PM
Quote
Ok the log3 version works fine.
Wonderful!Quote
Something I had not noticed before is I recieve an error about "Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." when I compile the project.
That warning should only come up if the project uses an IP core that is LogicLock'd. The mining firmware obviously doesn't so ... perhaps you fiddled with some strange setting? Or it might say it for no reason at all...I put the project I used up on the public GitHub repo, so you can try compiling that:
https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/BeMicro
Just pull the whole repo and compile the project under that BeMicro folder.
February 19, 2012, 06:07:57 AM
Ok the log3 version works fine. I have made one unit.
Start up
http://i1139.photobucket.com/albums/n553/Askit2/start.png
Running
http://i1139.photobucket.com/albums/n553/Askit2/running.png
I am not worried about the Rejected as it appears that Mining script only submits difficulty 1 shares. Will point it to a different pool for hopefully some successful hashing.
Something I had not noticed before is I recieve an error about "Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." when I compile the project. If I convert the SOF file to a JIC file and flash the Flash memory is it possible that it will run or will my lack of subscription mess that up I wonder? (just me wondering aloud. Subscription issue is possibly far more problematic.)
Works fine on bitclockers. Not complaining as of now I have 4 shares it has made and I will continue to enjoy this. Thank you so much for giving me a file that works. I am pretty sure that I can not learn how to use FPGA's for this without a license as of now. I can always try learning something else on it later.
Start up
http://i1139.photobucket.com/albums/n553/Askit2/start.png
Running
http://i1139.photobucket.com/albums/n553/Askit2/running.png
I am not worried about the Rejected as it appears that Mining script only submits difficulty 1 shares. Will point it to a different pool for hopefully some successful hashing.
Something I had not noticed before is I recieve an error about "Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." when I compile the project. If I convert the SOF file to a JIC file and flash the Flash memory is it possible that it will run or will my lack of subscription mess that up I wonder? (just me wondering aloud. Subscription issue is possibly far more problematic.)
Works fine on bitclockers. Not complaining as of now I have 4 shares it has made and I will continue to enjoy this. Thank you so much for giving me a file that works. I am pretty sure that I can not learn how to use FPGA's for this without a license as of now. I can always try learning something else on it later.
February 19, 2012, 04:59:35 AM
Quote
I am using the BeMicro-SDK, The tcl mining script, and unoptimized 115 pipelined with the cyclone IV chip programmed in to match my board.
Wow, Arrow really worked hard to make it extraordinarily difficult to find the right downloads for the BeMicro. 
Did you adjust the design to connect to the 50MHz clock on pin E1?
I took the time to set up a project and compile some firmware for you. Here is the SOF file:
http://www.bitcoin-mining.com/bemicro_loop4_50MHz_3MH_20120219a.sof
Please try that firmware, and then try the mining script again. If you can, take some screenshots of the mining script starting, running for a little bit, and any errors you might encounter.
Also, that firmware will only find a share every 24 minutes or so (on average). I modified the firmware to use LOOP_LOG2=3, which runs at 6MH/s (twice as fast):
http://www.bitcoin-mining.com/bemicro_loop3_50MHz_6MH_20120219a.sof
Should work just as well, but find a share every 12 minutes (on average).
February 19, 2012, 02:56:55 AM
I am using the BeMicro-SDK, The tcl mining script, and unoptimized 115 pipelined with the cyclone IV chip programmed in to match my board.
Edit: I am unable to monitor the chip with signal tap II it appears that either the script will run or I can run Signal tap II.
Edit 2: If I am reading mine.tcl correctly I should, as long as something is being done, get a hashrate on the miner window. Is it possible the data is never recieved from the FPGA? Is there a way to test the mining firmware with a console to force it to check one value maybe letting me know where to look for a problem? Or at least some way of sending some data and making sure i recieve something back?
Edit: I am unable to monitor the chip with signal tap II it appears that either the script will run or I can run Signal tap II.
Edit 2: If I am reading mine.tcl correctly I should, as long as something is being done, get a hashrate on the miner window. Is it possible the data is never recieved from the FPGA? Is there a way to test the mining firmware with a console to force it to check one value maybe letting me know where to look for a problem? Or at least some way of sending some data and making sure i recieve something back?
February 19, 2012, 01:38:53 AM
Hello Askit2! It is unclear to me what development board you are currently using. Are you using a DE0-Nano or a different board?
February 17, 2012, 06:00:10 PM
I am using the mining script that is in the project under scripts, miner. For the FPGA I have compiled the DE2_115_Unoptimized_Pipelined Loop_log2 set to 4 so it fits. Under synthesis after compilation I see optimization results folder under that I see registers removed during Synthesis. All are marked NonceXXX where XXX is a number and are moved to a DATAXX where XX is a number. It is likely normal but I am new and unsure. I am sure that even at 500Khash/s I should have one share in less then 12 hours. The FPGA seems warm for a bit when I start the mining script but after maybe an hour or so it gets to where plastic isn't warm. I am guessing that the warm is because FPGA is doing some processing and the cold is when it isn't processing. I am just unsure what part to look into to find out why it either isn't returning a value when done or why it stops trying. Mining script finds my miner. Starts up I think just fine. The unit never finishes in a positive way(no shares generated).
Adding SignaltrapII to see what is happening. Not sure what values it is supposed to monitor. I am going to watch the isGoldenTicket and the last 3 virtual wire ones.
Adding SignaltrapII to see what is happening. Not sure what values it is supposed to monitor. I am going to watch the isGoldenTicket and the last 3 virtual wire ones.
February 17, 2012, 05:26:18 PM
Hm, without knowing what code you are actually using, it should be ok with the pasting. As far i understand the miner gets some 'base data' apends the nonce starting a 0x00000000 und tries in the whole string gives a valid hash, and if that is found it returns the value of this particular nonce.
February 17, 2012, 04:39:40 PM
I think I have something in Quartus II setup wrong. Using 11.0 SP1 and after compiling I have 0 errors. I can program the chip. I can run the mining script and it detects the BeMicro-SDK. It puts out times then just 0s in all columns after that for I think my longest run so far is 10 hours.
I noticed that in the synthesis section it merged some nonce#'s to data. Will that make my FPGA not return a valid nonce? If so what do I do to get the values to stay as they are setup?
I noticed that in the synthesis section it merged some nonce#'s to data. Will that make my FPGA not return a valid nonce? If so what do I do to get the values to stay as they are setup?
February 15, 2012, 02:04:14 AM
Quote
Thanks again for the tip. It is quite possible that I will be near Irvine,CA,USA on April 24th, 2012.
https://www.weboom.com/avnet2012/
Neat! Thank you for digging up the link. Looks like the "Irvine" event is actually up in Orange https://www.weboom.com/avnet2012/
. See you guys there! Jump to: