2) Will the TCL script handle multiple instances of the miner within a single FPGA?
I tried to build an image with two instances of
fpgaminer_top but it did not change anything. Seems like the tcl scripts can only handle a single GNON/NONC interface. So I guess the answer is no here as well.
You could just use different ident strings for the second instance eg STA1/DAT1/GNO1/NON1 and STA2/DAT2/GNO2/NON2
(they seem to need to be 4 chars not longer), then duplicate the jtag driver code to direct the work alternately between them.
At a very long shot you might even try just running two instances of the mine.tcl scripts (in separate directories due to dependancies) and just change the idents accordingly. I don't know if this is supported by the quartus_stp driver, but I have had some success with this approach on another project.
[EDIT]
Actually, thinking about this, its a pretty crude approach. It would be better to rewrite
fpgaminer_top so as to apportion work between multiple hashers, and queue the results for transmission back via a single channel. Rather beyond my skills I'm afraid. I'll also note that the quartus_stp JTAG driver is not entirely reliable. I've had the mine.tcl script drop out with errors on extended runs (this is partly why I went the route of a custom serial interface to my raspberry pi host).
[EDIT2]
Then again it would be ridiculously easy just to push the same midstate_buf and data_buf into two or more sha256_transform units and just use different nonce values (eg for four instances just hardwire the top two bits of the nonce and count over a 30 bit range). Then just load golden_nonce based on whichever unit matches. Voila. You'd probably also need to reduce the getwork from every 20 seconds to something a bit faster in order to avoid wrapping and duplicating work. Longpoll would be nice too.
[EDIT3]
This is roughly what I had in mind
https://github.com/kramble/DE0-Nano-BitCoin-Miner/blob/master/Misc/quad_fpgaminer_top.v... just as a discussion point. I can't vouch for it working and it needs optimization, but I have given it a quick trip through the simulator (just tested one of the cores). I also found LX150_makomk_dualcore in the fpgaminer distribution which may be worth a look.
Anyway, with the rate that ASIC's are coming on stream and pushing up the difficulty, I doubt if anyone is going to do any further work on the fpgaminer code.
Mark