Fair enough. Xilinx likes to show off huge gate counts with lots of zeros. It is very misleading.
I've been looking for a good excuse to dust off my Verilog books and old Digilent Spartan 2e 200K board, maybe I can fit a serialized version on it.
Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013) - page 45. (Read 432950 times)
June 01, 2011, 02:21:41 AM
I've been looking for a good excuse to dust off my Verilog books and old Digilent Spartan 2e 200K board, maybe I can fit a serialized version on it.
May 31, 2011, 02:37:32 PM
Fair enough. Xilinx likes to show off huge gate counts with lots of zeros. It is very misleading.
I've been looking for a good excuse to dust off my Verilog books and old Digilent Spartan 2e 200K board, maybe I can fit a serialized version on it.
May 31, 2011, 05:31:56 AM
My apologies, then. I haven't done much with Altera chips; I don't know how the footprints convert from Xilinx's units.
Fair enough. Xilinx likes to show off huge gate counts with lots of zeros. It is very misleading.
May 31, 2011, 05:30:55 AM
Digilent has a few Xilinx 100K+ gate boards, in that range.
http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA
http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA
The 1200K gate board has less LEs than the DE0-Nano and costs $189.
My apologies, then. I haven't done much with Altera chips; I don't know how the footprints convert to Xilinx's units.
May 31, 2011, 05:25:21 AM
Digilent has a few Xilinx 100K+ gate boards, in that range.
http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA
http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA
The 1200K gate board has less LEs than the DE0-Nano and costs $189.
May 31, 2011, 05:11:33 AM
There is also a great Pull request that was submitted a day or two ago. It allows the design to scale down to fit into smaller chips, which I know a lot of people have been waiting for. I'm just waiting for some free time to open up so I can dive in, test the new patch out, and merge it. Many thanks to udif for submitting such a wonderful improvement!
Excellent.
Does anyone know of a board under $100 with more LEs (or equivalent arbitrary unit) than the DE0-Nano?
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593
I'm looking for a board for various student projects - near-free mining should help pay off the board.
Digilent has a few Xilinx 100K+ gate boards, in that range.
http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA
May 31, 2011, 04:03:11 AM
Quote
fpgaminer, what do you think about this Spartan-6
That's a XC6SLX100T-3CSG484I, which isn't quite the chip you'd want for mining. T isn't needed, since miners don't need transceivers. The best choices are XC6SLX###-3N in the cheapest package you can get. The XC6SLX150-3N can be had for $120 it seems, but I don't know for sure what the order quantity was for that. -3 was $130. May 31, 2011, 03:51:36 AM
fpgaminer, what do you think about this Spartan-6
I'm currently attempting to synthesize a design for it. From what it looks like, you could likely clock this thing at >100MHz, but it's a bit too small to host a full 133-stage mining pipeline. So you might want to go for the LX150T variant instead, possibly at a lower speed grade for cost efficiency reasons, I'll try the LX150T-3 and LX150T-2 variants later today. May 31, 2011, 03:49:39 AM
There is also a great Pull request that was submitted a day or two ago. It allows the design to scale down to fit into smaller chips, which I know a lot of people have been waiting for. I'm just waiting for some free time to open up so I can dive in, test the new patch out, and merge it. Many thanks to udif for submitting such a wonderful improvement!
Excellent.
Does anyone know of a board under $100 with more LEs (or equivalent arbitrary unit) than the DE0-Nano?
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593
I'm looking for a board for various student projects - near-free mining should help pay off the board.
May 31, 2011, 03:18:31 AM
seems to be almost as large as the virtex-5 above.
But I wonder about internal clk frequency on the Spartan compared to Virtex?
Price is going in the right direction though :-P
We really don't need a large capsule with lots of legs for this application.
I/O speed is also not very important.
But I wonder about internal clk frequency on the Spartan compared to Virtex?
Price is going in the right direction though :-P
We really don't need a large capsule with lots of legs for this application.
I/O speed is also not very important.
May 30, 2011, 10:34:43 AM
I'm relatively new to this, and have no idea how these blocks are constructed, so I fail at "calculate the midstate" and "generate the data", as I have no idea where to get the binary data of the block.
Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
I will do it for free, just PM me an email address and I will send you two or three "checking values" that I have from beforehand Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
May 30, 2011, 10:11:47 AM
fpgaminer, what do you think about this Spartan-6
May 30, 2011, 09:00:14 AM
I'm relatively new to this, and have no idea how these blocks are constructed, so I fail at "calculate the midstate" and "generate the data", as I have no idea where to get the binary data of the block.
Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
i could do it for you for say 10btc.Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
its very precise and complex work.
and its requirer alot of time, and experienced.
so 10btc is relatively cheap.
May 30, 2011, 08:15:43 AM
I'm relatively new to this, and have no idea how these blocks are constructed, so I fail at "calculate the midstate" and "generate the data", as I have no idea where to get the binary data of the block.
Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
May 30, 2011, 08:12:22 AM
I did manage to synthesize a design for an xc5vlx110t-1ff1136 (which I had sitting around anyway) running at 120MH/s in the meantime. I chose to not use JTAG for communication, and implemented a simple RS232 interface instead.
The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.
Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?
can't you just not make your own, it should not be too hard:The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.
Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?
pick a known block.
calculate the midstate.
generate the data.
extract the nonce.
done!
May 30, 2011, 05:24:41 AM
I did manage to synthesize a design for an xc5vlx110t-1ff1136 (which I had sitting around anyway) running at 120MH/s in the meantime. I chose to not use JTAG for communication, and implemented a simple RS232 interface instead.
The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.
Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?
The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.
Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?
May 28, 2011, 07:52:02 PM
Quote
Good job, fpgaminer. Just donated 1 BTC.
Thank you lzsaver! That's really great Quote
Anyone port this over to a Xilinx chip yet?
I've got a branch of the project on my system that replaced the PLL and probes for Xilinx chips. ISE is giving me trouble though, and won't fully route the design. So it wasn't a one-night port like I had hoped 
But I am working on it and will of course update the repo when the code is working.I've mainly been tinkering with a WizNet module hooked up to the DE2-115 board, allowing the board to mine all on its own without a PC.
There is also a great Pull request that was submitted a day or two ago. It allows the design to scale down to fit into smaller chips, which I know a lot of people have been waiting for. I'm just waiting for some free time to open up so I can dive in, test the new patch out, and merge it. Many thanks to udif for submitting such a wonderful improvement!
May 28, 2011, 06:58:25 PM
Anyone port this over to a Xilinx chip yet? I have a couple of different Xilinx-series boards I can borrow, but I'm too much of a verilog n00b to replace altpll and altsource_probe with vendor-neutral equivalents 
I've just started working on a rewrite in VHDL for Xilinx FPGAs during the last hours.While this is nowhere near finished, things look promising so far
May 28, 2011, 04:01:55 AM
Anyone port this over to a Xilinx chip yet? I have a couple of different Xilinx-series boards I can borrow, but I'm too much of a verilog n00b to replace altpll and altsource_probe with vendor-neutral equivalents
May 26, 2011, 09:41:53 PM
Good job, fpgaminer. Just donated 1 BTC.
Jump to: