Re: Stratix-5 A7 or D5 project 01.05.2013 update - page 3.

funnow

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Quote from: turtle83 on April 21, 2013, 04:01:34 PM

Quote from: kingcoin on April 21, 2013, 03:56:43 PM

Quote from: funnow on April 21, 2013, 12:12:45 PM

kingcoin -> for now I can only say thank you. I have to talk with some potential investors in the project, so for now I can't pay you for your help.

No problem. I did not expect to get payed. These are very expensive FPGA's. In general the cheaper FPGA's will usually get you higher H/s/$. But of course I don't know what kind of deal you can get.

I would be very curious to know what khash/s it could achieve for LTC. Nobody has (atleast in public) claimed to be mining LTC with FPGA.

I dont know much about FPGA or embedded programming, but from what i read, scrypt is very sensitive to the amount of fast RAM available to the cores.. The new expensive FPGAs apparently have them in abundance..

Further reading: http://bitcoin.stackexchange.com/questions/1305/what-features-of-scrypt-make-tenebrix-gpu-resistant

You could be curious, and you will remain curious, because It's a bitcoin project.

kingcoin

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Quote from: funnow on April 21, 2013, 05:58:32 AM

Virtex-7 -> It will not be used!

I don't know why you ruled out the Virtex7. I just gave the biggest member (xc7v2000t) of the Virtex7 family a run through Vivado. I constrained the clocks at 200MHz and the timing was reported as 4.575ns or 218Mhz. The utilization of a single core was

Code:

+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Loced | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 44753 | 0 | 1221600 | 3.66 |

Hence it might be possible to fit 27 hash cores (- logic to communicate with the cores) in the device which would lead to a hashing performance of 5.8Gh/s assuming timing would be the same for 27 cores. Others on the forum have optimized the design using the Xilinx DSP blocks (this device has 2160 of them) and did run the Kintex7 at much higher frequencies. This is a very expensive FPGA. But again, I don't know what kind of deal you can get.

phk

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Quote from: kingcoin on April 21, 2013, 10:54:21 AM

Quote from: phk on April 21, 2013, 09:06:57 AM

For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.

BTW: was this the design found in the rtl directory or in some of the projects?

I will try to re-run it as my timing result can't be correct...

It sounds like you have since sorted it out, but yes I was using a cloned DE2-115 project which refers to the common ../../src/xxx.v

I just changed the target device and created a new PLL.

turtle83

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Supersonic

Quote from: kingcoin on April 21, 2013, 03:56:43 PM

Quote from: funnow on April 21, 2013, 12:12:45 PM

kingcoin -> for now I can only say thank you. I have to talk with some potential investors in the project, so for now I can't pay you for your help.

No problem. I did not expect to get payed. These are very expensive FPGA's. In general the cheaper FPGA's will usually get you higher H/s/$. But of course I don't know what kind of deal you can get.

I would be very curious to know what khash/s it could achieve for LTC. Nobody has (atleast in public) claimed to be mining LTC with FPGA.

I dont know much about FPGA or embedded programming, but from what i read, scrypt is very sensitive to the amount of fast RAM available to the cores.. The new expensive FPGAs apparently have them in abundance..

Further reading: http://bitcoin.stackexchange.com/questions/1305/what-features-of-scrypt-make-tenebrix-gpu-resistant

kingcoin

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Quote from: funnow on April 21, 2013, 12:12:45 PM

kingcoin -> for now I can only say thank you. I have to talk with some potential investors in the project, so for now I can't pay you for your help.

No problem. I did not expect to get payed. These are very expensive FPGA's. In general the cheaper FPGA's will usually get you higher H/s/$. But of course I don't know what kind of deal you can get.

kingcoin

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Activity: 262

Merit: 250

Quote from: kingcoin on April 21, 2013, 10:54:21 AM

Quote from: phk on April 21, 2013, 09:06:57 AM

For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.

BTW: was this the design found in the rtl directory or in some of the projects?

I will try to re-run it as my timing result can't be correct...

I checked my design and my clock was not properly constrained due to a syntax error in my SDC file. I ran it with the corrected SDC file.The result is still not great: 185.84 MHz. Again, it was the plain unrolled design from the "rtl" directory without any specific optimization. However, the speed difference could be due to the difference between the C1 and the C2 device.

funnow

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kingcoin -> for now I can only say thank you. I have to talk with some potential investors in the project, so for now I can't pay you for your help.

kingcoin

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Merit: 250

Quote from: phk on April 21, 2013, 09:06:57 AM

For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.

BTW: was this the design found in the rtl directory or in some of the projects?

I will try to re-run it as my timing result can't be correct...

kingcoin

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Quote from: phk on April 21, 2013, 09:06:57 AM

Quote from: kingcoin on April 21, 2013, 06:44:18 AM

A simple compile using Quartus 12.1 of the unoptimized design(1) in a A7 device gives the following result:

; Device ; 5SGXEA7K2F40C2 ;
; Logic utilization (in ALMs) ; 32,617 / 234,720 ( 14 % ) ;

For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.
The only change I made was a new PLL megafunction.

I have a serial interface and some other communication logic in there which can explain the extra ALM's.

200MHz Fmax on the hash clock? That's more what I would expect, or even faster for such a device. Did you use derive_pll_clocks and derive_clock_uncertainty in the SDC file for your timing analysis?

phk

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Quote from: kingcoin on April 21, 2013, 06:44:18 AM

A simple compile using Quartus 12.1 of the unoptimized design(1) in a A7 device gives the following result:

; Device ; 5SGXEA7K2F40C2 ;
; Logic utilization (in ALMs) ; 32,617 / 234,720 ( 14 % ) ;

For what it's worth, I used 5SGXEA7H1F35C1 and got 11% utilization (~8 cores?), and Fmax >200MHz.
The only change I made was a new PLL megafunction.

funnow

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Quote from: kingcoin on April 21, 2013, 06:44:18 AM

Quote from: funnow on April 21, 2013, 05:58:32 AM

Virtex-7 -> It will not be used!
So Stratix V A7 or maybe Stratix V D5 -> will be used

A simple compile using Quartus 12.1 of the unoptimized design(1) in a A7 device gives the following result:

; Device ; 5SGXEA7K2F40C2 ;
; Logic utilization (in ALMs) ; 32,617 / 234,720 ( 14 % ) ;

In this device you should fit at least 6 miners, more if you can share resources and use the dsp blocks.

A 10ns clock gives a slack of -1.9ns, which pretty bad performance. I don't understand why.

1) git://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner.git

Before you start making a PCB you should get the tools to explore implementations and do simulations to make sure your implementation is working, also you would probably want to get a dev kit to play with before you design your own PCB. They come with schematics so you can see how things are done, even though that they are somewhat overengineered and have lots of stuff you don't need like serdes, pcie, ddr3 interfaces and so on.

Thanks for help.
It will be not easy to develop a good pcb... I have a friend who knows something about FPGA, but He is busy with other projects.

kingcoin

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Quote from: funnow on April 21, 2013, 05:58:32 AM

Virtex-7 -> It will not be used!
So Stratix V A7 or maybe Stratix V D5 -> will be used

A simple compile using Quartus 12.1 of the unoptimized design(1) in a A7 device gives the following result:

; Device ; 5SGXEA7K2F40C2 ;
; Logic utilization (in ALMs) ; 32,617 / 234,720 ( 14 % ) ;

In this device you should fit at least 6 miners, more if you can share resources and use the dsp blocks.

A 10ns clock gives a slack of -1.9ns, which pretty bad performance. I don't understand why.

1) git://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner.git

Before you start making a PCB you should get the tools to explore implementations and do simulations to make sure your implementation is working, also you would probably want to get a dev kit to play with before you design your own PCB. They come with schematics so you can see how things are done, even though that they are somewhat overengineered and have lots of stuff you don't need like serdes, pcie, ddr3 interfaces and so on.

funnow

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Quote from: kingcoin on April 21, 2013, 05:45:58 AM

Quote from: funnow on April 21, 2013, 03:43:07 AM

Quote from: kingcoin on April 21, 2013, 03:40:36 AM

Which Stratix7 and ArriaV do you have in mind?

Did I miss something? Are those new chips? Never mentioned any Arria series chip. And nowhere is mentioned Stratix - VII

Sorry brainfart. Which chip in the Virtex7 and StratixV families did you have in mind?

Virtex-7 -> It will not be used!
So Stratix V A7 or maybe Stratix V D5 -> will be used

kingcoin

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Quote from: funnow on April 21, 2013, 03:43:07 AM

Quote from: kingcoin on April 21, 2013, 03:40:36 AM

Which Stratix7 and ArriaV do you have in mind?

Did I miss something? Are those new chips? Never mentioned any Arria series chip. And nowhere is mentioned Stratix - VII

Sorry brainfart. Which chip in the Virtex7 and StratixV families did you have in mind?

Signus

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Quote from: funnow on April 21, 2013, 03:43:07 AM

Quote from: kingcoin on April 21, 2013, 03:40:36 AM

Which Stratix7 and ArriaV do you have in mind?

Did I miss something? Are those new chips? Never mentioned any Arria series chip. And nowhere is mentioned Stratix - VII

I'm not sure what he means either. I think only Stratix V is the newest model.

Quote from: funnow on April 21, 2013, 03:29:12 AM

Quote from: Signus on April 21, 2013, 03:14:07 AM

I do understand, and it's fine to learn.

Do you have any experience handling electronics? If not, I suggest reading up on soldering SMT and through-hole components. And one of my favorite books for FPGA's is Embedded Design Using Programmable Gate Arrays by Dennis Silage. Very useful.

Both chips are roughly the same price, aside from the distributors. How many chips do you plan on buying? Minimal quantities will run you thousands per chip. My sources on that one are Digikey and Altera.

If you buy 25k I imagine you can get them at a fraction of the cost, but buying a single chip would break bank unless you're rolling in dough, haha.

I have a little experience in handling electronics, much more I have in computer repairing (about 30 years) but If I will need someone, there is a friend company doing this and they probably help me. Yeah similar prices, but Stratix-5 +5% of hashrate and little more power usage,...
I have sources in CHN (one of my friends moved in China) so If I find any good price, he checks the company,..... Single chip will be bought only for test, but I'm still doing some research about this part.
And as I see maybe my post is somehow interesting (see a lot of you is reading this) -> also helping me, and I can only say thanks.
Maybe the first batch will be about 15k, maybe more. But first I have to find some computer for gold refining (lol) to have a bigger $ cap (he he)

Okay, and I would love to be of assistance, I have experience with FPGA's and embedded design. Just not the funds to get my hands on good equipment. Even my University won't buy me anything good for my research.

If he finds you a good rate, let me know. I have heard a lot of people ordering chips or FPGA's from HK and so much so that it's almost ridiculous the kind of savings they're getting. I want to know because I'll be investing a lot of money developing FPGA's in the future.

funnow

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Quote from: kingcoin on April 21, 2013, 03:40:36 AM

Which Stratix7 and ArriaV do you have in mind?

Did I miss something? Are those new chips? Never mentioned any Arria series chip. And nowhere is mentioned Stratix - VII

kingcoin

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Which Stratix7 and ArriaV do you have in mind?

funnow

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Activity: 347

Merit: 100

Quote from: Signus on April 21, 2013, 03:14:07 AM

I do understand, and it's fine to learn.

Do you have any experience handling electronics? If not, I suggest reading up on soldering SMT and through-hole components. And one of my favorite books for FPGA's is Embedded Design Using Programmable Gate Arrays by Dennis Silage. Very useful.

Both chips are roughly the same price, aside from the distributors. How many chips do you plan on buying? Minimal quantities will run you thousands per chip. My sources on that one are Digikey and Altera.

If you buy 25k I imagine you can get them at a fraction of the cost, but buying a single chip would break bank unless you're rolling in dough, haha.

I have a little experience in handling electronics, much more I have in computer repairing (about 30 years) but If I will need someone, there is a friend company doing this and they probably help me. Yeah similar prices, but Stratix-5 +5% of hashrate and little more power usage,...
I have sources in CHN (one of my friends moved in China) so If I find any good price, he checks the company,..... Single chip will be bought only for test, but I'm still doing some research about this part.
And as I see maybe my post is somehow interesting (see a lot of you is reading this) -> also helping me, and I can only say thanks.
Maybe the first batch will be about 15k, maybe more. But first I have to find some computer for gold refining (lol) to have a bigger $ cap (he he)

Signus

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Activity: 28

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I do understand, and it's fine to learn.

Do you have any experience handling electronics? If not, I suggest reading up on soldering SMT and through-hole components. And one of my favorite books for FPGA's is Embedded Design Using Programmable Gate Arrays by Dennis Silage. Very useful.

Both chips are roughly the same price, aside from the distributors. How many chips do you plan on buying? Minimal quantities will run you thousands per chip. My sources on that one are Digikey and Altera.

If you buy 25k I imagine you can get them at a fraction of the cost, but buying a single chip would break bank unless you're rolling in dough, haha.

funnow

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Merit: 100

Quote from: Signus on April 20, 2013, 02:30:43 PM

Quote from: funnow on April 19, 2013, 12:34:42 PM

Quote from: Signus on April 19, 2013, 12:29:28 PM

Yeah for some reason I was thinking Spartan 6, was half asleep.

As far as the Virtex-7 goes, and the bandwith that chip is capable of it can produce roughly ~1GH/s to maybe 3GH/s. It's a very beefy chip, and also very expensive. I'm talking $4000 a chip.

The Stratix 5 I'm not quite sure. I don't see any numbers as far as chip bandwidth goes, but it's outrageously expensive per chip as well.

So I don't know how low of a price you're trying to negotiate, or where from. I'm curious as to why you would consider the investment if you aren't an Engineer or don't have one?

I'm not an engineer and I don't have any. No problem, we are human and we have to make mistakes.
Yeah Virtex-7 is a good one. And Kintex-7? It could be possible the 7K410T series could make about 750mhash/s?
Thanks again.

Well my point is that you not an Engineer nor do you have one, and yet you're thinking about investing thousands of dollars on a product you have no idea how to design? The Virtex-7 and Stratix-5 are very expensive chips, and the only way you can afford them per chip is to by them tens of thousands at a time. Assuming you have a design in the first place.

Even without being an Engineer you should realize the pricepoint of what you want to do is very very high.

I have excluded Virtex-7, so the project will be with Stratix-5. And if I'm not or I don't have an Engineer, It doesn't mean that I can't do a project

And believe me the price would not be high.

Topic: Re: Stratix-5 A7 or D5 project 01.05.2013 update - page 3. (Read 6610 times)