Topic: s9 > batch 16 and Auto-Tune Issues - page 2. (Read 5435 times)
I know most folks don't really take stuff apart, but can someone confirm whether or not the new-batch S9 boards have the U2 digital potentiometer populated? The ones I've looked at from older batches don't, and I haven't seen any adjustments in voltage during startup so I wonder if these aren't made for a fixed core voltage. The new ones look to be adjusting voltage on the fly, like S7 boards should have been capable of, so either they're doing something unexpected or that dpot should be on there.
So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Grant you so far we have few data points but -- correct.For the old miners, if the original/older firmware works then I say do not upgrade. Most of my miners except the B1 (changed to low voltage version) are running the firmware they shipped with.
As for applying the new firmware to the batch-16/17 miners, I am going to wait a bit to see any problems other folks have before *maybe* upgrading.
So it would seem like upgrading to the latest FW on the website on old miners is not advisable right now is that the general agreement here?
Ouch!!!!
One trick I learned after munging a s9 Frimware: Unplug the PCI power to the hash boards and power only the controller.
Power up, wait several min and see if the Bitmain GUI reports life (socket connection error goes away).
If no go, still only with controller power, press the reset button for ~ 10sec then release it. Wait several more min to see if it lives. If it is alive you should be able to set pools, etc even without the hash boards working.
If it comes back to life, power down, reconnect power to hash boards and pray everything works....
One trick I learned after munging a s9 Frimware: Unplug the PCI power to the hash boards and power only the controller.
Power up, wait several min and see if the Bitmain GUI reports life (socket connection error goes away).
If no go, still only with controller power, press the reset button for ~ 10sec then release it. Wait several more min to see if it lives. If it is alive you should be able to set pools, etc even without the hash boards working.
If it comes back to life, power down, reconnect power to hash boards and pray everything works....
stupid as i am i did the firmware upgrade and this is all that happens now.
PS: its been like this for hours, ive done a few reboots too, and factory reset etc.
http://i63.tinypic.com/2ez1vh1.png
anyone got a older firmware file for s9 b9 ?
PS: its been like this for hours, ive done a few reboots too, and factory reset etc.
http://i63.tinypic.com/2ez1vh1.png
Code:
Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01397ea4 ends at 0x01398000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 56:d9:6b:09:dc:23
init phy ok
PHY DMA init OK
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
chain[0] has no freq in PIC! Will use default freq=600 and jump over...
chain[2] has no freq in PIC! Will use default freq=600 and jump over...
chain[3] has no freq in PIC! Will use default freq=600 and jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
disable_pic_dac on chain[0] testDone[0]=1
disable_pic_dac on chain[2] testDone[2]=1
disable_pic_dac on chain[3] testDone[3]=1
search freq for 1 times, completed chain = 3, total chain num = 3
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
Miner fix freq ...
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do 12 8xPatten test for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=897 on chain[0]
now set pic voltage=79 on chain[0]
use PIC voltage=897 on chain[2]
now set pic voltage=79 on chain[2]
use PIC voltage=897 on chain[3]
now set pic voltage=79 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 62
Error: The AsicNum=62 on chain[3]!
Set Freq of PIC for Test Patten on Chain[0]
Set Freq of PIC for Test Patten on Chain[2]
Set Freq of PIC for Test Patten on Chain[3]
set_baud=1
Initializing cgroup subsys cpuset
Linux version 3.10.31-ltsi-00003-gcf03eb9 (lzq@armdev01) (gcc version 4.7.3 20121106 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2012.11-20121123 - Linaro GCC 2012.11) ) #81 SMP Mon Apr 25 11:20:36 CST 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 258048
free_area_init_node: node 0, pgdat 806e5cc0, node_mem_map 8072a000
Normal zone: 2016 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 258048 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @80f17000 s11200 r8192 d13376 u32768
pcpu-alloc: s11200 r8192 d13376 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 256032
Kernel command line: mem=1008M console=ttyS0,115200 root=/dev/mtdblock3 rw rootfstype=jffs2
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 1008MB = 1008MB total
Memory: 1015844k/1015844k available, 16348k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xbf800000 - 0xff000000 (1016 MB)
lowmem : 0x80000000 - 0xbf000000 (1008 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x8065a930 (6475 kB)
.init : 0x8065b000 - 0x806adbc0 ( 331 kB)
.data : 0x806ae000 - 0x806e9990 ( 239 kB)
.bss : 0x806e9990 - 0x80729384 ( 255 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1196.85 BogoMIPS (lpj=5984256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17687 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x804ab220 - 0x804ab278
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated (1196.85 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 524288 B
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti
PTP clock support registered
Switching to clocksource timer0
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled for 1 cores
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 1984
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
denali-nand-dt ff900000.nand: Dump timing register values:acc_clks: 4, re_2_we: 20, re_2_re: 20
we_2_re: 12, addr_2_data: 14, rdwr_en_lo_cnt: 2
rdwr_en_hi_cnt: 2, cs_setup_cnt: 2
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
5 ofpart partitions found on MTD device denali-nand
Creating 5 MTD partitions on "denali-nand":
0x000000000000-0x000001000000 : "NAND Flash Boot Area 16MB"
0x000001000000-0x000002000000 : "NAND Flash Boot Area backup1 16MB"
0x000002000000-0x000003000000 : "NAND Flash Boot Area backup2 16MB"
0x000003000000-0x00000b000000 : "NAND Flash jffs2 Root Filesystem 128MB"
0x00000b000000-0x000010000000 : "NAND Flash jffs2 Root Filesystem 80MB"
dw_spi_mmio fff00000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=bf8dc000, irq=163)
stmmac_hw_init: 1000M
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 0007c0f1 at 0 IRQ POLL (stmmac-0:00) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: couldn't determine pwr-en, assuming pwr-en = 0
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data width, 1024 deep fifo
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 400000Hz, actual 396825HZ div = 63)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 300000Hz, actual 297619HZ div = 84)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 200000Hz, actual 200000HZ div = 125)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000Hz, actual 100000HZ div = 250)
jffs2: Empty flash at 0x01397ea4 ends at 0x01398000
VFS: Mounted root (jffs2 filesystem) on device 31:3.
devtmpfs: mounted
Freeing unused kernel memory: 328K (8065b000 - 806ad000)
eth0: device MAC address 56:d9:6b:09:dc:23
init phy ok
PHY DMA init OK
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
In axi fpga driver!
Original value in RESET_MANAGER_BASE_ADDR + BRGMODRST_ADDR is 0x0
request_mem_region OK!
AXI fpga dev virtual address is 0xbf942000
*base_vir_addr = 0xc504
In fpga mem driver!
request_mem_region OK!
fpga mem virtual address is 0xc0000000
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
eth0: device MAC address 00:1d:6c:ed:31:bf
init phy ok
PHY DMA init OK
IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
libphy: stmmac-0:00 - Link is Up - 100/Full
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
chain[0] has no freq in PIC! Will use default freq=600 and jump over...
chain[2] has no freq in PIC! Will use default freq=600 and jump over...
chain[3] has no freq in PIC! Will use default freq=600 and jump over...
set command mode to VIL
singleBoardTest: AsicType = 1387
singleBoardTest: asicNum = 64
singleBoardTest: real AsicNum = 63
--- check asic number
set_baud=1
The min freq=700
set real timeout 52, need sleep=379392
disable_pic_dac on chain[0] testDone[0]=1
disable_pic_dac on chain[2] testDone[2]=1
disable_pic_dac on chain[3] testDone[3]=1
search freq for 1 times, completed chain = 3, total chain num = 3
restart Miner chance num=2
waiting for send_func to exit of chain[0]
waiting for send_func to exit of chain[1]
waiting for send_func to exit of chain[2]
waiting for send_func to exit of chain[3]
waiting for send_func to exit of chain[4]
waiting for send_func to exit of chain[5]
waiting for send_func to exit of chain[6]
waiting for send_func to exit of chain[7]
waiting for send_func to exit of chain[8]
waiting for send_func to exit of chain[9]
waiting for send_func to exit of chain[10]
waiting for send_func to exit of chain[11]
waiting for send_func to exit of chain[12]
waiting for send_func to exit of chain[13]
waiting for send_func to exit of chain[14]
waiting for send_func to exit of chain[15]
waiting for receive_func to exit!
waiting for pic heart to exit!
Start bmminer ...
Chain[J1] has no freq in PIC, set default freq=600M
Chain[J1] has no core num in PIC
Chain[J3] has no freq in PIC, set default freq=600M
Chain[J3] has no core num in PIC
Chain[J4] has no freq in PIC, set default freq=600M
Chain[J4] has no core num in PIC
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
Miner fix freq ...
read PIC voltage=897 on chain[0]
Chain:0 chipnum=63
Chain[J1] voltage added=0.0V
Chain[J1] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:0 temp offset=0
Chain:0 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:0 max freq=600
Chain:0 min freq=600
read PIC voltage=897 on chain[2]
Chain:2 chipnum=63
Chain[J3] voltage added=0.0V
Chain[J3] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:2 temp offset=0
Chain:2 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600 Asic[62]:600
Chain:2 max freq=600
Chain:2 min freq=600
read PIC voltage=897 on chain[3]
Chain:3 chipnum=62
Chain[J4] voltage added=0.0V
Chain[J4] [minerMAC: 00:1d:6c:ed:31:bf hashMAC: 00:00:00:00:00:00]
Chain:3 temp offset=0
Chain:3 base freq=100
Asic[ 0]:600
Asic[ 1]:600 Asic[ 2]:600 Asic[ 3]:600 Asic[ 4]:600 Asic[ 5]:600 Asic[ 6]:600 Asic[ 7]:600 Asic[ 8]:600
Asic[ 9]:600 Asic[10]:600 Asic[11]:600 Asic[12]:600 Asic[13]:600 Asic[14]:600 Asic[15]:600 Asic[16]:600
Asic[17]:600 Asic[18]:600 Asic[19]:600 Asic[20]:600 Asic[21]:600 Asic[22]:600 Asic[23]:600 Asic[24]:600
Asic[25]:600 Asic[26]:600 Asic[27]:600 Asic[28]:600 Asic[29]:600 Asic[30]:600 Asic[31]:600 Asic[32]:600
Asic[33]:600 Asic[34]:600 Asic[35]:600 Asic[36]:600 Asic[37]:600 Asic[38]:600 Asic[39]:600 Asic[40]:600
Asic[41]:600 Asic[42]:600 Asic[43]:600 Asic[44]:600 Asic[45]:600 Asic[46]:600 Asic[47]:600 Asic[48]:600
Asic[49]:600 Asic[50]:600 Asic[51]:600 Asic[52]:600 Asic[53]:600 Asic[54]:600 Asic[55]:600 Asic[56]:600
Asic[57]:600 Asic[58]:600 Asic[59]:600 Asic[60]:600 Asic[61]:600
Chain:3 max freq=600
Chain:3 min freq=600
max freq = 600
prepare send works thread on chain[0]
prepare send works thread on chain[1]
prepare send works thread on chain[2]
prepare send works thread on chain[3]
prepare send works thread on chain[4]
prepare send works thread on chain[5]
prepare send works thread on chain[6]
prepare send works thread on chain[7]
prepare send works thread on chain[8]
prepare send works thread on chain[9]
prepare send works thread on chain[10]
prepare send works thread on chain[11]
prepare send works thread on chain[12]
prepare send works thread on chain[13]
prepare send works thread on chain[14]
prepare send works thread on chain[15]
do 12 8xPatten test for 1 times
Find hashboard on Chain[0]
Find hashboard on Chain[2]
Find hashboard on Chain[3]
use PIC voltage=897 on chain[0]
now set pic voltage=79 on chain[0]
use PIC voltage=897 on chain[2]
now set pic voltage=79 on chain[2]
use PIC voltage=897 on chain[3]
now set pic voltage=79 on chain[3]
enable_pic_dac on chain[0]
enable_pic_dac on chain[2]
enable_pic_dac on chain[3]
set command mode to VIL
doHeatBoard: AsicType = 1387
doHeatBoard: asicNum = 64
doHeatBoard: real AsicNum = 63
--- check asic number
check chain[0]: asicNum = 63
check chain[2]: asicNum = 63
check chain[3]: asicNum = 62
Error: The AsicNum=62 on chain[3]!
Set Freq of PIC for Test Patten on Chain[0]
Set Freq of PIC for Test Patten on Chain[2]
Set Freq of PIC for Test Patten on Chain[3]
set_baud=1
anyone got a older firmware file for s9 b9 ?
According to Bitmain support, this firmware is for all S9`s. look at the description of the file: Antminer-S9-all-201610180851-autofreq-user.tar
Be very careful updating your S9`s some of mine went mental in chip temp and I had to flash with older bios, something is very wrong with this bios.
Be very careful updating your S9`s some of mine went mental in chip temp and I had to flash with older bios, something is very wrong with this bios.
Has anyone tried the "bypass the fan pwm control line to give constant 100%" trick?
I wonder how much it would freak out if you used an external PWM fan driver and piped through the tach line so it would still see the fan spinning?
Yup, I am thinking of something like that. Right now I have noticed that the tuning process can complete with only one fan online, while the other is unplugged. But bmminer stops immediately after tuning completes, and puts out an error message, when it detects a single fan. 
I wonder how much it would freak out if you used an external PWM fan driver and piped through the tach line so it would still see the fan spinning?
Yup, I am thinking of something like that. Right now I have noticed that the tuning process can complete with only one fan online, while the other is unplugged. But bmminer stops immediately after tuning completes, and puts out an error message, when it detects a single fan.
I wonder how much it would freak out if you used an external PWM fan driver and piped through the tach line so it would still see the fan spinning?
Considering how long this autotune stuff takes, it would make a lot more sense if you could do it once and then re-use the conf file it created. Ideally you should be able to choose to use manual settings or use the autotune file and if the autotune file doesn't exist then you hit a button to go through the process and generate one. It shouldn't need to do this every single time. It would also make sense if you could at least raise the fan speed higher than the autotune level.
Can someone please post their Config.ini It's in /etc/config directory of the miner.
You can ssh in to the miner user:root password:admin
TIA
You can ssh in to the miner user:root password:admin
TIA
Here's my Config.ini
Here's part of what's being tested
Code:
[Config]
Name=S9 HASH board
TestDir=/etc/config/minertest64/minertest64_
DataCount=912
PassCount1=912
PassCount2=912
PassCount3=912
Freq=600
Timeout=0
OpenCoreGap=50000
# about temperature
CheckTemp=0
# GetTempFrom 0: get from LM75A through IIC, 1: get from ASIC
GetTempFrom=1
TempSel=0
TempSensor1=62
TempSensor2=0
TempSensor3=0
TempSensor4=0
DefaultTempOffset=-70
StartSensor=62
StartTemp=0
#AsicInterval can only changed by developer
CoreNum=114
AsicNum=63
TestMode=0
CheckChain=1
Open_Core_Num1=4294967295
Open_Core_Num2=4294967295
Open_Core_Num3=4294967295
Open_Core_Num4=262143
#CommandMode 0:vil 1:fil
CommandMode=0
AsicType=1387
ValidNonce1=57456
ValidNonce2=57456
ValidNonce3=57456
#Pic
Pic_VOLTAGE=1
#Pic_VOLTAGE=0
IICPic=1
DAC=1
UseConfigVol=1
Voltage1=860
Voltage2=860
Voltage3=860
Voltage4=0
Voltage_e=10
final_voltage1=910
final_voltage2=910
final_voltage3=910
#Time
year=2016
month=5
date=18
hour=10
minute=36
second=12
freq_gap=0
UseFreqPIC=1
freq_e=0
freq_m=5
freq_a=0
freq_t=1000
force_freq=0
Here's part of what's being tested
Code:
head minertest64_01.txt
midstate 54f4143b58a1aa726126f05a0e139cc77c8704b0f964492c5dedc72c4bf2c295 data 08fb04182215d0573d3c794d nonce 00c11e80
midstate 23070884132238d15b9965654e70f12d0bc65b2397bac907a2a32e6a717b457f data 08fb04182215d057e4e72139 nonce 00bb2f81
midstate 834c5dc6b512794da705ec87e6e623ef39c1445282f697f21cfe67300374f14f data 08fb04182215d0573ed12131 nonce 0030cc82
midstate c04f66c8f6cb80da6da15a65fad6fd6bb251634191e1ed07d9f9604fb01e3197 data 08fb04182215d05743cdd12a nonce 0017e383
midstate d317ad116e4d7785789605513bad64c3ee657b420a80d7c8d397a2504dacad14 data 08fb04182215d0578bd858c5 nonce 005d1e84
midstate 3088e2a0ed8b9e5d3d62426006f8cccac0701bdae371272ed2374d20d9332e81 data 08fb04182215d057b9c4274e nonce 006cb205
midstate d3c85b944335e3ac7eb3843a3dab00aa9ce0705104e70d421442a91aeecddb78 data 08fb04182215d057956835fe nonce 00b48806
midstate 1bcd4b9fd2780d76a527576d3eb70f55e3522321e33eaf811127798afad88a3e data 08fb04182215d05744ce32b4 nonce 00000b87
midstate 176bf295a43209b74174466e12832c5609fa3cb317618e7a1279416c6e5891d5 data 08fb04185915d05715033365 nonce 002a4f08
midstate 3c2777dc334efbe51cf9c6f772ff8fc6e8e1725186ef16ed184b9d68eb1768f9 data 08fb04185915d05719c73399 nonce 00b7a409
I received my Antminer S9 Batch 17 today. It takes almost 30 minutes to start mining. Meanwhile the fans are running loud and produce a weird harmonic, which is irritating at best.
I was snooping around a bit by sshing into the miner.
Looks like at bootup, the miner writes fresh config files and then runs a process called
single-board-test then runs scores of test possibly to characterise the ASIC chips; which was the output being seen in the Kernel log.
Finally bmminer is instantiated to start mining.
bmminer, first sets fan PWM to 100 then reduces it to 30. It's still plenty loud at 30. It would be good to be able to manually control the fan speed.
I was snooping around a bit by sshing into the miner.
Looks like at bootup, the miner writes fresh config files and then runs a process called
Code:
single-board-test
single-board-test then runs scores of test possibly to characterise the ASIC chips; which was the output being seen in the Kernel log.
Finally bmminer is instantiated to start mining.
Code:
/usr/bin/bmminer --version-file /usr/bin/compile_time --api-listen --default-config /config/bmminer.conf
bmminer, first sets fan PWM to 100 then reduces it to 30. It's still plenty loud at 30. It would be good to be able to manually control the fan speed.
Looking through the Kernel Log raises some questions for me. For one, just how granular is the Auto-tuning that Bitmain introduced? The end of the log shows many new things...
Along with the ASIC strings on the board running different frequencies, the gods forbid, is EACH ASIC's speed different as well?? Sure looks like it to me otherwise what's the point of recording per-chip speeds? Is it even possible to do that (different speed per-ASIC)? I'd think that it would raise hell with timing the data xfrs...
If this is the case then the boards reported speed is the average of all speeds being used on the board.
Code:
read PIC voltage=870 on chain[6]
Chain:6 chipnum=63
Chain[J7] voltage added=0.1V
OK: Chain[J7] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:6 temp offset=-70
Chain:6 base freq=568
Asic[ 0]:600
Asic[ 1]:650 Asic[ 2]:650 Asic[ 3]:618 Asic[ 4]:650 Asic[ 5]:650 Asic[ 6]:625 Asic[ 7]:650 Asic[ 8]:650
Asic[ 9]:650 Asic[10]:650 Asic[11]:650 Asic[12]:587 Asic[13]:650 Asic[14]:650 Asic[15]:650 Asic[16]:650
Asic[17]:575 Asic[18]:650 Asic[19]:568 Asic[20]:650 Asic[21]:650 Asic[22]:637 Asic[23]:650 Asic[24]:650
Asic[25]:650 Asic[26]:618 Asic[27]:650 Asic[28]:650 Asic[29]:637 Asic[30]:650 Asic[31]:650 Asic[32]:650
Asic[33]:650 Asic[34]:650 Asic[35]:625 Asic[36]:650 Asic[37]:631 Asic[38]:650 Asic[39]:643 Asic[40]:650
Asic[41]:650 Asic[42]:650 Asic[43]:650 Asic[44]:650 Asic[45]:650 Asic[46]:650 Asic[47]:643 Asic[48]:618
Asic[49]:650 Asic[50]:650 Asic[51]:650 Asic[52]:631 Asic[53]:650 Asic[54]:650 Asic[55]:650 Asic[56]:650
Asic[57]:650 Asic[58]:568 Asic[59]:650 Asic[60]:568 Asic[61]:650 Asic[62]:650
Chain:6 max freq=650
Chain:6 min freq=568
read PIC voltage=870 on chain[7]
Chain:7 chipnum=63
Chain[J8] voltage added=0.1V
OK: Chain[J8] is for this machine! [minerMAC: 00:13:f0:a4:b2:1b]
Chain:7 temp offset=-70
Chain:7 base freq=537
Asic[ 0]:575
Asic[ 1]:656 Asic[ 2]:625 Asic[ 3]:575 Asic[ 4]:656 Asic[ 5]:656 Asic[ 6]:575 Asic[ 7]:656 Asic[ 8]:656
Asic[ 9]:581 Asic[10]:656 Asic[11]:656 Asic[12]:593 Asic[13]:656 Asic[14]:656 Asic[15]:656 Asic[16]:656
Asic[17]:650 Asic[18]:656 Asic[19]:650 Asic[20]:656 Asic[21]:656 Asic[22]:656 Asic[23]:537 Asic[24]:656
Asic[25]:656 Asic[26]:581 Asic[27]:656 Asic[28]:656 Asic[29]:650 Asic[30]:656 Asic[31]:550 Asic[32]:656
Asic[33]:631 Asic[34]:656 Asic[35]:656 Asic[36]:656 Asic[37]:537 Asic[38]:656 Asic[39]:656 Asic[40]:643
Asic[41]:656 Asic[42]:656 Asic[43]:643 Asic[44]:562 Asic[45]:656 Asic[46]:656 Asic[47]:650 Asic[48]:656
Asic[49]:656 Asic[50]:656 Asic[51]:656 Asic[52]:568 Asic[53]:656 Asic[54]:631 Asic[55]:625 Asic[56]:656
Asic[57]:656 Asic[58]:556 Asic[59]:656 Asic[60]:575 Asic[61]:656 Asic[62]:656
Chain:7 max freq=656
Chain:7 min freq=537
Along with the ASIC strings on the board running different frequencies, the gods forbid, is EACH ASIC's speed different as well?? Sure looks like it to me otherwise what's the point of recording per-chip speeds? Is it even possible to do that (different speed per-ASIC)? I'd think that it would raise hell with timing the data xfrs...
If this is the case then the boards reported speed is the average of all speeds being used on the board.
I have two older miners with older firmware.
I also have one spare controller with older firmware.
I am waiting on a hashboard and one more controller.
I also have one spare controller with older firmware.
I am waiting on a hashboard and one more controller.
I have a miner with a problematic board (an earlier batch, like 3 or something) and I have to reboot it many times to get a decent hashrate from the problem hashboard. If the reboot process took a lot longer, that sounds like a pain in the ass. Unless this process actually guaranteed a good boot from that board. I am skeptical though.
Supposedly new firmwares are going to be available on the website for download soon so I would guess they will be releasing this kind of thing to buyers of earlier batches.
Supposedly new firmwares are going to be available on the website for download soon so I would guess they will be releasing this kind of thing to buyers of earlier batches.
Just got a s9 batch-17 and... Bitmain has changed the firmware.
Looks like changing the frequency may be gone. There is no longer a GUI option to change it. On startup, the firmware goes through several checks per-board and sets the best freq and possibly Vcore as well per-board. When all is done, the boards report different frequencies. This could turn out to be rather -- interesting.
Looks like changing the frequency may be gone. There is no longer a GUI option to change it. On startup, the firmware goes through several checks per-board and sets the best freq and possibly Vcore as well per-board. When all is done, the boards report different frequencies. This could turn out to be rather -- interesting.
How Spondoolies-ish - though without the voltage adjust feature from the SP20....
Auto-tuning is a good idea, but only if it's an option and not a mandate. There should be manual control of everything, with an automatic everything as an optional setting.
Course, I think the same thing about cars and nobody pays attention to that either.
Course, I think the same thing about cars and nobody pays attention to that either.
Is there a fixed hash rate which is achieved by the miner setting up different freqs per board? (best working settings per board)
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