"Damned if you do, damned if you don't!" is said very often here.
But "Damned if you do it not right!" would fit much better in this case.
Why did KnC publish these technical slides without any comments? In this way they say almost nothing about the feasibility of their concept and the overall project status. Just a nice slide show to let customers with no or little technical background feel good. This automatically causes a lot of wild speculation. So why not add enough information to make the slides self-explanatory, e.g.:
Slide 2: ASIC schematic
192 (48 x 4) engine IP cores (pipelined SHA256 hash cores, one hash per clock cycle)
-> running at minimum
[email protected] to realize 100 GH/s per die (could be higher in case of defect cores)
Slide 3: ASIC Toplevel Floorplan View
-> ASIC requires hierarchical layout flow to handle complexity (millions of standard cells)
-> complex engine IP (multi-million gates) "hardened" first; seen as multiple instantiated cells at ASIC toplevel
-> 0.6 mm2 per engine IP results in about 115 mm2 die size
(BTW: PLL arrow points to wrong location, should be probably rectangle with red halo at the right side)
Slide 4: Engine IP floorplan
-> engine IP hardened 2x with different shapes for area optimization at toplevel
-> bigger notch of 2nd engine IP macro used as placement area for PLL at toplevel (2nd macro placed 2 times at the right side of each quad)
-> "magic" pattern caused by timing driven placement of standard cells related to pipeline stages; just a funny visual effect
Slide 7: Thermal simulation
-> Assumption: 200W power consumption (based on worst case power analysis @ 1.0V & 30 % over clocked)
-> Simulation result: die junction temperature does not exceed 125C
Disclaimer: These are no official KnC information. Just a proposal and educated guesses of an ASIC design engineer how to publish such stuff in a more professional way. Anyway, the most important question regarding the project schedule and the feasibility of the announced start date for delivery is:
When was the tape-out of the ASIC executed? If not executed yet, when is the tape-out planned for?