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Topic: Ultra-Low-Cost DIY FPGA Miner - 175MH/s @ $1/MH - page 7. (Read 125892 times)

rph
full member
Activity: 176
Merit: 100
What is that program you are running?  Looks neat and cool!

It's called mpbm and it's GPL'd. It's pretty sweet!

-rph
hero member
Activity: 756
Merit: 500
What is that program you are running?  Looks neat and cool!



FPGA mining has come a long way since September.
Arsbitcoin needs to fix their service  Tongue but with multi-pool support it's not a big issue.
Thanks again to TheSeven for his awesome miner SW.

-rph


rph
full member
Activity: 176
Merit: 100
we are eager to reproduce your configuration somehow.

heh, the more the merrier!

-rph
aTg
legendary
Activity: 1358
Merit: 1000
Honestly, this is the only serious and well thought out project that exists now to create a cluster bitcoin FPGA.
I hope you continue to finish up, we are eager to reproduce your configuration somehow.
rph
full member
Activity: 176
Merit: 100


FPGA mining has come a long way since September.
Arsbitcoin needs to fix their service  Tongue but with multi-pool support it's not a big issue.
Thanks again to TheSeven for his awesome miner SW.

-rph

rph
full member
Activity: 176
Merit: 100
have you decided to sell these yet?

If you're interested in a 10GH/s+ cluster - that could start to make sense - PM me and we can discuss.
I don't want FPGAs to become too widely available.. I want to compete with 45nm GPUs forever   Grin

-rph
legendary
Activity: 2128
Merit: 1073
i run 5 smartXplorer iterations one time, and each take 2~2.5GB of RAM
Thank you for your input. I resolved to stop using my 4GB RAM machines for any serious future work. Because of my stupidity I installed the FPGA design software on a laptop that cannot be upgraded beyond 4GB. I need to re-think my planned computer purchases.

This is a link for future reference:

http://www.xilinx.com/ise/products/memory.htm

I wish I read and understood it before I rushed to install the Design Suite.
hero member
Activity: 592
Merit: 501
We will stand and fight.
have you decided to sell these yet?

MR. heavyb looks like seek for a fpga mining system for quite a while.  Grin
full member
Activity: 217
Merit: 100
have you decided to sell these yet?
hero member
Activity: 592
Merit: 501
We will stand and fight.
so a i7-2600 with 16GB ram can finish 0-100 table in 1-2days.  Grin
Did you run 4 smartXplorer iterations on a same CPU taking advantage of the quad-core? Or a single iteration took 16GB of RAM to implement a single Spartan-6 design?

i run 5 smartXplorer iterations one time, and each take 2~2.5GB of RAM
legendary
Activity: 2128
Merit: 1073
so a i7-2600 with 16GB ram can finish 0-100 table in 1-2days.  Grin
Did you run 4 smartXplorer iterations on a same CPU taking advantage of the quad-core? Or a single iteration took 16GB of RAM to implement a single Spartan-6 design?
rph
full member
Activity: 176
Merit: 100
but be careful, when you run @ 190 Mhz, the chip will easily to get over heat, any heat dissipation method form chip's top is useless . particularly you are using a 2 layers PCB.

Yup, that is good advice. xpa gave me a max ambient of -47.4C with no heatsink. 21.6W with 50% toggle rate.  Shocked

-rph
hero member
Activity: 592
Merit: 501
We will stand and fight.
smartXplorer   Grin

Indeed. But that only removes the last 20-30k of the timing score. The rest is attempting random
VHDL tweaks until you magically trigger an efficient placement. It is really time consuming work.

-rph


my experience is manually limit the running time to less than 2hr, i discovered when the "magically table" has been triggered, the P&R will finish very fast. so a i7-2600 with 16GB ram can finish 0-100 table in 1-2days.  Grin


ADD:

but be careful, when you run @ 190 Mhz, the chip will easily to get over heat, any heat dissipation method form chip's top is useless . particularly you are using a 2 layers PCB.
rph
full member
Activity: 176
Merit: 100
smartXplorer   Grin

Indeed. But that only removes the last 20-30k of the timing score. The rest is attempting random
VHDL tweaks until you magically trigger an efficient placement. It is very time consuming work.

-rph
hero member
Activity: 592
Merit: 501
We will stand and fight.
After some quality time with the Xilinx build tools, I'm up to 192MH/s in -3.
I think this is the second-fastest published result (about 8MHz behind ztex)

I'm on track to have the cluster built in around 3-4 weeks. Would have been
like late Oct, but the business/sales side of buying the FPGAs took foreeeeeever.

-rph


smartXplorer   Grin
rph
full member
Activity: 176
Merit: 100
After some quality time with the Xilinx build tools, I'm up to 192MH/s in -3.
I think this is the second-fastest published result (about 8MH/s behind ztex).

I'm on track to have the cluster built in around 3-4 weeks. Would have been
like late Oct, but the business/sales side of buying the FPGAs took foreeeeeever.

-rph
rph
full member
Activity: 176
Merit: 100
A couple people asked about the PCB vendors I've been using -
here are the two main ones:

DorkbotPDX
Seeedstudio

Dorkbot uses a US fab, with gold-plating, extremely high quality, 2 wk turn, and they
have a 4-layer service, but they are pretty expensive for large boards.
I'll be using Seeedstudio for the carriers.

It's awesome to have two options for low cost, low vol PCBs now.

-rph
rph
full member
Activity: 176
Merit: 100
I say this because I love to participate in the development of an FPGA cluster but I see that everyone develops their own hardware and not much collaboration.

There was an open source FPGA miner effort, but it pretty much stalled when some of the
most talented contributors left & started their own project.

-rph
aTg
legendary
Activity: 1358
Merit: 1000
Why not release the circuit diagram?

IMO open source hardware (of this complexity) doesn't work economically. To build qty 1 would cost probably
$400+ due to the low-volume PCB fabrication, low volume BGA assembly (unless you do this yourself),
2-3X higher pricing on low qty parts orders, shipping costs from 3-4 different distributors, etc.

To get good $/MH you really need a single entity building the design in high quantity --
either an individual building a large 10GH/s+ rig, or a company willing to invest the capital and
accept the risk and customer support issues/etc to resell them in lower qtys.

-rph


I do not think we understand each other, to begin forgiveness for my English translator ...

Releasing the diagram to the research staff member, not that any company produce it.
There are some ideas that we could certainly provide interesting, your idea of ​​making an adapter between the chip and the motherboard seems very good but not larger than 4 FPGAs would be interesting to reduce the number of pins? or if not possible, it would be better aligned horizontally or use a vertical slot type?

I say this because I love to participate in the development of an FPGA cluster but I see that everyone develops their own hardware and not much collaboration.
sr. member
Activity: 437
Merit: 250
Also, is that 1, or 4 FPGAs?

kicad, and 4 sockets for the FPGA modules.

-rph


Hmm... never heard of it /me adds to growing list of circuit building software

And... wow /nerdgasm

I really, really wish I had more disposable income, because something like this would be awesome to be able to support
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