Topic: wild and unsubstantiated speculation about BFL's power woes - page 4. (Read 6345 times)

They already said they probably have to add an external power supply plus heatsink and fan to the Jalapeno.

That means they can throw away lots of existing Jalapeno casings and PCBs. And burnt lots of our pre order money for this "Lessons Learned".

The fact that only recently "discovered" the real power consumption of their ASICS shows that they never had a working prototype up until now.

What were those fuckers supposed to ship in October 2012 (their original shipping date) ? They had nothing back then. Literally nothing! Stringing customers along for months ...

AT that point you have a 40watt idle board powering a 4.5GH/s device.

As originally designed yes.  But with an external power brick and the original regulators (though more of them) it should work fine.  It would need a heatsink as well, but again, they could still reuse those boards and components related to the original mini single SC.

Looking at the video and picture posted, I have a hard time believing the problem just lies outside the chips if the power meter in Luke's pictures is accurate at 180W. Even if it's only 150W DC, there just isn't anything else on the board that could handle dissipating that kind of heat with minimal airflow other than the big heat sink. Even with those little heat sinks on the power fets and under the board, there's no way even half of that 150W is being dissipated in the board. The chips themselves are almost definitely running at several times higher than their estimated efficiency, and it's unlikely they're going to be able to solve that just with board changes.

Could you please speculate wildly on why the idle power usage is so high?
The ratio of loaded/idle is unlike anything CMOS that I have ever seen. It reminds me of ECL or linear analog designs.

How can one get to such predicament? I've heard of latchup in CMOS circuits, but it becomes a short circuit and therefore completely prevents the normal operation until powered down.

The jalapeno is powered by 2 x 2.5 watt USB plugs. It was originally intended to be 4.5GH/s and 4.5 watt, but if the chips are more than 12% out of spec, the jalapeno will not run at all at 4.5GH/s. You're right though, they're saying the problem isn't the chips, it's the regulator, blah blah blah, but the jalapeno boards were considerably less populated than the other boards. They lacked a lot of the power handling stuff, the capacitors and such, that the larger boards have. You would think if it was a board problem, not a chip problem, the jalapeno wouldn't be affected, and they would be flying out the door.

Powered by unicorn blood generators :/ ....

Is there a way to speculate what one chip will use in power?

Wild speculation....

The could still use existing boards and chips to make Jallys. 

could someone explain to a noob how they could potentialy archive a cut in power this large?
Dissabling chips (hashing engines), Underclocking, Undervolting and more Regulators won't do the trick i think

I'm not sure that this is their first prototype. If it is, they had more luck than they deserve.

I assume they made one or more runs that where not working at all. If they spend enough money they might be able to create a cooling that is able to cool down the chips. I assume they will not invest in a cooling solution with a price of several thousand dollars in order to cool down a single. At the moment they are in a trap. They promised too much and have no product they can afford to deliver. Trying another ASIC run and shift the shipment by another several months will hit them very hard with Avalon creating one batch after the other.

It's also entirely possible that they never simulated anything, that they're flying by the seat of their pants, and their first prototype is educating them on why you don't go whole hog and order the parts to mass produce a product before any testing is done.

Let's not forget this is their FIRST PHYSICAL PROTOTYPE. Yes, the results they are getting would be a problem if they were nearing mass production, but they are still in the very early stages with their FIRST PHYSICAL PROTOTYPE.

The chips are ok....it's the board that is the problem....so they say.

They are doing a revision on the PCB & adding "power regulators" or something  

Congrats on the "devil" post #666 

Disclaimer: I don't know anything that hasn't been posted here in the forum, and I have been too busy to read more than 5-10% of that, I have no inside info, this is just speculation based on past chip design experience, yadda yadda.

It sounds like BFL is having some difficulties with their chips (a) running at ~25% of rated speed and (b) consuming 4-9x more power than they planned.  These numbers are vague since the info in the postings I've come across has always been patchy and has been presented very poorly (they'll quote an actual hashrate but decline to say what device it came from, or show a photo of a kill-a-watt but decline to say exactly what's plugged into it, etc).  I would welcome a simple and straightforward posting by BFL saying "we have the chips running at X% of advertised speed and consuming Y J/GH".

They've also mentioned that the wafer-probing tests (which I assume ran only a tiny portion of one chip at a time due to the fact that unpackaged chips overheat when run at full speed) produced the power results they expected, but the packaged chips consume way too much power.

I'm going to make a wild guess here and speculate that they ran all their pre-production SPICE simulations using the default 25 degree C temperature.

This is a pretty common mistake.  It would also explain everything I've seen so far.

Circuits always simulate ridiculously well if you run SPICE at 25 degrees.  The problem is that any circuit doing substantial amounts of computation will generate enough heat to raise the local temperature to at least 100 degrees C.  This in turn reduces the power efficiency even further (circuits running hot run slower and burn more power), an effect that feeds on itself.  Even the best packaging and heatsinking still leaves 3-4 degrees C per watt, and often those figures neglect to include the thermal resistivity of the CMOS bulk (another few degrees C per watt).  Multiply all of that by a 10-20W chip and the junction temperature is going to be a lot closer to 100-110 degrees than 25 degrees in any sort of reasonable ambient temperature.

Repeated disclaimer: this is just a wild guess, I have almost zero information, I have been way too busy with other urgent crap to read most of the forum threads, etc, etc.