Topic: [WIP] Lunch-Box-48 -{small time avalon based miner}- - page 2. (Read 16905 times)
Watching. Be interesting to see peeps custom cases further down the line.
Do you mean you will show a design blueprint here one day or do you offer something other like assembly, diy-kits or similar?
What is the purpose of this thread?
Documenting and sharing my work on an Avalon based miner. Including design choices and the reasons for them.
Ofcourse you are free to point and laugh, but please post your reasons, I might learn something.
Can I use your designs?
Yes you can, though I would like to be credited.
Sounds easy, and FREE! What's the catch?
If you want to sell products based on my design, I'll give an address where you can donate.
I want to see 3d pictures of your design!
I can't promise sketchup pictures, I need more training to use it properly.
Okay, get to it then.
I'm already at it. Some stuff is not that far along, so that will be a bit empty for the time being. This post is a work in progress as well.
Edit:
Here is the link to Github of this project
_______________________________________________________________________________ ___________
Lunch-Box-48
Conception
I bought 48 avalon chips in t13hydra's groupbuy and I have to put them somewhere to work in 8 to 10 weeks. Klondike and BitBurner are fun designs, but I'm an engineer, I want to design my own boards.
I wanted to stay as compatible to the regular avalon rig as possible. Though cgminer would have to start with another flag, "--avalon-options 115200:24:10:45:282" is the default. I hope the current firmware accepts changes to the second and third number. Ending up at something like this: "--avalon-options 115200:12:4:45:282".
So I'll be using the FPGA and wr703n.
What's in a name
I was looking for a name, but at first ended up a 'cherry island', Avalon could mean 'Apple island' according to wikipedia. So a cherry is a smaller fruit than an apple, you get the picture...
But looking at the enclosure I chose, it kinda reminded me of an oversized lunch box. Adding the number 48 is simply a reference to the number of avalon chips.
Design method
Schematic design and PCB layouting are my strong points. I also do some VHDL and C. I like FPGA's, to bad the Avalon team can't publish the VHDL yet as there is some proprietry stuff in there. So I'll be forced to use their bitstream for the BGA packaged FPGA, If I had the VHDL I could trim out a lot of excess IO's so I could migrate to a TQFP-144 package. I love handsoldering those.
Anyway, I work from the outside in. Starting at the enclosure, to module placement, to board design and cabling.
The work is divided in different sections, the enclosure as the top level, the boards are the sublevels. I will discuss these seperatly and ad my thoughts, concerns, ideas, doubts, etc..
Design tree
Enclosure->
-> tl-wr703n
-> Controller board
-> ASIC cards
-> Connector board
_______________________________________________________________________________ ___________
Enclosure
Hammond 1402K has got about 230x238x93mm internal space. Aluminum. pdf
PSU 150W open frame 12V 91~93% efficiëncy. Type: Iccnexergy FSA150012A. pdf
- A bit expensive but has high power density (watt per cm3) 127.0mm x 76.2mm x 30.9mm
Decent power entry, a combination of socket, fuse and switch would be good, I think. 06A2D by Delta electronics link
two fans attached to front panel, if they fit, pick 92mm, else 80mm. Mechanical vibration could be problematic in this enclosure. (add fanfilters)
modify front and back panel with a multitool(dremel).
Controller board
Connector board
four ASIC cards
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
tl-wr703n
I need a modified tl-wr703n to run the standard Avalon firmware.
- I can buy a premodified one on ebay. It has the 64MB RAM chip. link
I still need to modify it so it can be powered from the device side. According to the wiki I should populate R113 with a 0R resistor to do it.
Also an external antenna is preferable, so an SMA connector mod needs to be done aswell. Several distributors offer chassis mounted SMA connectors wth a cable already attached to it, quite handy. ebay
- I've got a metal enclosure, should the antenna ground/shield be electrically connected to it? Yes (tentative)
A 9dBi antenna would be nice, doesn't seem to use the 5.8GHz band, so the antenna doesn't need to be specified for that. Example ebay
38cm is a bit long, perhaps I won't need all that gain? 7dBi is 19,5cm.
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
Controller board
Designed to be ordered at PCBpool.
4layer with decent specs to fully break out the 256bga FPGA package.
Stackup:
l1 0,018mm
prepreg 0,38mm
l2 0,035mm
core 0,71mm
l3 0,035mm
prepreg 0,38mm
l4 0,018mm
Based on the reference design. Aiming for about 80x80mm size.
Separate board which could be replaced with a cheaper one when the VHDL becomes opensource.
- Is the HUB chip necissary? tl-wr703n has USB issues, perhaps they are solved by this? Not sure yet. Gonna place it anyway.
- Connect all the data lines to the connectors? We could save space and time. But future modifications might need more data channels. Not sure yet.
- Can the current bitstream handle unconnected datalines? external pullups for the unused report lines? Yes it can, as you can run the original with fewer modules.
- Needs one temp sensor on board and the other on a heatsink. Temp sensor 1 is on the board, Temp sensor 2 or 3 could be used for the heatsink. 3 is standard.
- Connect the two fans to FAN2 and FAN3
- Replace the fuse with an active current limiting chip on the USB B port connected to the tl-wr703n. Do the same with the downstram facing port of the hub.
- Reuse the powersupply designs from the ASIC cards for the 5V, 3,3V and 1,2V nets.
- As a connector use a straddle mount pci-express socket (4x) with 64 contacts.
- Use a voltage supervisor to handle the reset of the FPGA. STM6780TWB6F or similar. Instead of the standard RC network
Needs reflow soldering due to BGA package. Perhaps let someone else do it, or make/buy a reflow oven. (not sure yet)
- I've got a quote to have the FPGA mounted on two boards, cost €25 excluding shipping. (I asked for two boards cause i like to keep a backup board just in case)
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
ASIC cards
Designed to be ordered at Seeedstudios. 4layer 70x180mm
Stackup:
l1 0,035mm
prepreg 0,2mm
l2 0,018mm
core 1,2mm
l3 0,018mm
prepreg 0,2mm
l4 0,035mm
12 avalon chips per card, a 12V to 1,2V dc/dc smps per four chips.
There are three cheap standard 1/2brick sized heatsinks per card, each covering 4 avalons and it's smps. Heatsinks are about 60x60x25mm. Type 518-95AB by Wakefield.
PCI-express card edge connector is used for availability and cost.
- v-scoring board edges? Not necessary (tentative)
- locking cards in place? Standard board locks dont secure all angles. Perhaps a screw connection to secure them. Chose to go with simple scewable brackets to crew the cards onto the connector board.
Clock distribution. One 32MHz crystal ocillator outputting 3,3V CMOS. Going to a clock buffer/splitter, with high rise and fall times, to go to the three groups of 4 chips.
Those chips in a group will have their clock daisychained and terminated at the most remote point with an RC parallel termination. Need to properly caculate that.
- Think about layer use. Perhaps l1 = power, l2 = GND, l3 = data and clock, l4 = GND
Ground the heatsinks, or let them float? Float, to prevent RF current flow in the heatsink. (tentative)
Select a buck convertor that can supply 2A at 1,2V to each avalon chip.
Chip footprint conflict. Two documents in the avalon-ref github specify different pad sizes. The footprint from the datasheet was correct.
- Use a voltage supervisor to handle the reset of the ASIC. STM6780TWB6F or similar. Instead of the standard RC network
Update: SMPS designed, 90% efficiency Link to calculations
Update: Clock distribution designed. Went for a point to point solution in the end. Link to simulations
Update: I revised the clock distribution, while still point to point, it now uses cheaper parts.
Update: The auxiliary power supplies are designed and can be reused on the controller board. Link to post
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
Connector board
Designed to be ordered at Seeedstudios. 2layer 100x150mm (prelim)
A simple board which connects the controller board to the ASIC cards and to the PSU
Has four pci express connectors for the ASIC cards.
Connectors for the 12V
A connector for the controller board, not sure which one(s). Depends on the number of signals.
There are 24 lines going to the ASIC boards and 24 comming back. 48 in total.
I chose a straddle mount pci express x4 socket, that has 64 contacts. Surplus can be used for power.
_______________________________________________________________________________ ___________
Documenting and sharing my work on an Avalon based miner. Including design choices and the reasons for them.
Ofcourse you are free to point and laugh, but please post your reasons, I might learn something.
Can I use your designs?
Yes you can, though I would like to be credited.
Sounds easy, and FREE! What's the catch?
If you want to sell products based on my design, I'll give an address where you can donate.
I want to see 3d pictures of your design!
I can't promise sketchup pictures, I need more training to use it properly.
Okay, get to it then.
I'm already at it. Some stuff is not that far along, so that will be a bit empty for the time being. This post is a work in progress as well.
Edit:
Here is the link to Github of this project
_______________________________________________________________________________ ___________
Lunch-Box-48
Conception
I bought 48 avalon chips in t13hydra's groupbuy and I have to put them somewhere to work in 8 to 10 weeks. Klondike and BitBurner are fun designs, but I'm an engineer, I want to design my own boards.
I wanted to stay as compatible to the regular avalon rig as possible. Though cgminer would have to start with another flag, "--avalon-options 115200:24:10:45:282" is the default. I hope the current firmware accepts changes to the second and third number. Ending up at something like this: "--avalon-options 115200:12:4:45:282".
So I'll be using the FPGA and wr703n.
What's in a name
I was looking for a name, but at first ended up a 'cherry island', Avalon could mean 'Apple island' according to wikipedia. So a cherry is a smaller fruit than an apple, you get the picture...
But looking at the enclosure I chose, it kinda reminded me of an oversized lunch box. Adding the number 48 is simply a reference to the number of avalon chips.
Design method
Schematic design and PCB layouting are my strong points. I also do some VHDL and C. I like FPGA's, to bad the Avalon team can't publish the VHDL yet as there is some proprietry stuff in there. So I'll be forced to use their bitstream for the BGA packaged FPGA, If I had the VHDL I could trim out a lot of excess IO's so I could migrate to a TQFP-144 package. I love handsoldering those.
Anyway, I work from the outside in. Starting at the enclosure, to module placement, to board design and cabling.
The work is divided in different sections, the enclosure as the top level, the boards are the sublevels. I will discuss these seperatly and ad my thoughts, concerns, ideas, doubts, etc..
Design tree
Enclosure->
-> tl-wr703n
-> Controller board
-> ASIC cards
-> Connector board
_______________________________________________________________________________ ___________
Enclosure
Hammond 1402K has got about 230x238x93mm internal space. Aluminum. pdf
PSU 150W open frame 12V 91~93% efficiëncy. Type: Iccnexergy FSA150012A. pdf
- A bit expensive but has high power density (watt per cm3) 127.0mm x 76.2mm x 30.9mm
Decent power entry, a combination of socket, fuse and switch would be good, I think. 06A2D by Delta electronics link
two fans attached to front panel, if they fit, pick 92mm, else 80mm. Mechanical vibration could be problematic in this enclosure. (add fanfilters)
modify front and back panel with a multitool(dremel).
Controller board
Connector board
four ASIC cards
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
tl-wr703n
I need a modified tl-wr703n to run the standard Avalon firmware.
- I can buy a premodified one on ebay. It has the 64MB RAM chip. link
I still need to modify it so it can be powered from the device side. According to the wiki I should populate R113 with a 0R resistor to do it.
Also an external antenna is preferable, so an SMA connector mod needs to be done aswell. Several distributors offer chassis mounted SMA connectors wth a cable already attached to it, quite handy. ebay
- I've got a metal enclosure, should the antenna ground/shield be electrically connected to it? Yes (tentative)
A 9dBi antenna would be nice, doesn't seem to use the 5.8GHz band, so the antenna doesn't need to be specified for that. Example ebay
38cm is a bit long, perhaps I won't need all that gain? 7dBi is 19,5cm.
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
Controller board
Designed to be ordered at PCBpool.
4layer with decent specs to fully break out the 256bga FPGA package.
Stackup:
l1 0,018mm
prepreg 0,38mm
l2 0,035mm
core 0,71mm
l3 0,035mm
prepreg 0,38mm
l4 0,018mm
Based on the reference design. Aiming for about 80x80mm size.
Separate board which could be replaced with a cheaper one when the VHDL becomes opensource.
- Is the HUB chip necissary? tl-wr703n has USB issues, perhaps they are solved by this? Not sure yet. Gonna place it anyway.
- Connect all the data lines to the connectors? We could save space and time. But future modifications might need more data channels. Not sure yet.
- Can the current bitstream handle unconnected datalines? external pullups for the unused report lines? Yes it can, as you can run the original with fewer modules.
- Needs one temp sensor on board and the other on a heatsink. Temp sensor 1 is on the board, Temp sensor 2 or 3 could be used for the heatsink. 3 is standard.
- Connect the two fans to FAN2 and FAN3
- Replace the fuse with an active current limiting chip on the USB B port connected to the tl-wr703n. Do the same with the downstram facing port of the hub.
- Reuse the powersupply designs from the ASIC cards for the 5V, 3,3V and 1,2V nets.
- As a connector use a straddle mount pci-express socket (4x) with 64 contacts.
- Use a voltage supervisor to handle the reset of the FPGA. STM6780TWB6F or similar. Instead of the standard RC network
Needs reflow soldering due to BGA package. Perhaps let someone else do it, or make/buy a reflow oven. (not sure yet)
- I've got a quote to have the FPGA mounted on two boards, cost €25 excluding shipping. (I asked for two boards cause i like to keep a backup board just in case)
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
ASIC cards
Designed to be ordered at Seeedstudios. 4layer 70x180mm
Stackup:
l1 0,035mm
prepreg 0,2mm
l2 0,018mm
core 1,2mm
l3 0,018mm
prepreg 0,2mm
l4 0,035mm
12 avalon chips per card, a 12V to 1,2V dc/dc smps per four chips.
There are three cheap standard 1/2brick sized heatsinks per card, each covering 4 avalons and it's smps. Heatsinks are about 60x60x25mm. Type 518-95AB by Wakefield.
PCI-express card edge connector is used for availability and cost.
- v-scoring board edges? Not necessary (tentative)
- locking cards in place? Standard board locks dont secure all angles. Perhaps a screw connection to secure them. Chose to go with simple scewable brackets to crew the cards onto the connector board.
Clock distribution. One 32MHz crystal ocillator outputting 3,3V CMOS. Going to a clock buffer/splitter, with high rise and fall times, to go to the three groups of 4 chips.
Those chips in a group will have their clock daisychained and terminated at the most remote point with an RC parallel termination. Need to properly caculate that.
- Think about layer use. Perhaps l1 = power, l2 = GND, l3 = data and clock, l4 = GND
Ground the heatsinks, or let them float? Float, to prevent RF current flow in the heatsink. (tentative)
Select a buck convertor that can supply 2A at 1,2V to each avalon chip.
Chip footprint conflict. Two documents in the avalon-ref github specify different pad sizes. The footprint from the datasheet was correct.
- Use a voltage supervisor to handle the reset of the ASIC. STM6780TWB6F or similar. Instead of the standard RC network
Update: SMPS designed, 90% efficiency Link to calculations
Update: Clock distribution designed. Went for a point to point solution in the end. Link to simulations
Update: I revised the clock distribution, while still point to point, it now uses cheaper parts.
Update: The auxiliary power supplies are designed and can be reused on the controller board. Link to post
_______________________________________________________________________________ ___________
_______________________________________________________________________________ ___________
Connector board
Designed to be ordered at Seeedstudios. 2layer 100x150mm (prelim)
A simple board which connects the controller board to the ASIC cards and to the PSU
Has four pci express connectors for the ASIC cards.
Connectors for the 12V
A connector for the controller board, not sure which one(s). Depends on the number of signals.
There are 24 lines going to the ASIC boards and 24 comming back. 48 in total.
I chose a straddle mount pci express x4 socket, that has 64 contacts. Surplus can be used for power.
_______________________________________________________________________________ ___________
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