SMPS design for the asic cardsWelcome to the land of never ending tradeoffs, designing an SMPS. Choices effect parts of your design in unforseen ways.
Saving cost at one place increases cost somewhere else, same goes for efficency, transient response, ripple supression, etc... I'll try to find an optimum.
I maintain a maximum component hight of 10mm to allow space between ASIC cards. This will constrain filter component choice.
Why go through all this effort? Because I'm an EE and I like it.
Controller intersil isl6545 €2,40
Why this one?
It's cheap, runs at 300KHz and drives with the full vcc(12V) instead of a 5V from an internal LDO.
I go for low frequency because I assume that is best for these high current designs. The overall solution size will increase.
Stuff to calculate/pick:
Mosfets, output inductor, input and output capacitor, feedback, compensation and overcurrent protection.
Mosfet selectionI'll go for the Alpha and omega dual asymetric nmos line. Why this brand? It's cheap and well speced.
Why Asymetric? Top and bottom mosfets have diffrent requirements. Especially at low dutycycles. We're at 10%. (!)
The topfet(Q1) needs to switch fast, thus benefitting more from a low gate charge than lower Rds(on).
The lowerfet(Q2) conducts for 90% of the time, thus benifitting greatly from a lower Rds(on).
I'm going to use the 10Vgs Rds(on) values. That aproximates worst case for 12Vgs and allows for some margin.
I compared two, one with lower gate charge in the bottom mosfet than the other. Top fets are almost identical. Does the reduced Rds(on) wheigh up to the increased driver losses? And can the driver handle the extra dissapation?
Don't be mislead by gate capacitance values in datasheets, they are not fit for this calculation. (They specify at 0 Vgs)
I'm going to look at the Vgs to Qgate (Qtotal) graph and extrapolate the gate charge at 12V.
AON6973A - €0,86
Q1_Rds(on) = 4,3mOhm
Q2_Rds(on) = 3,1mOhm
extrapolated_Qgate(Q1) = 20nC
Cgate(Q1)=Qtotal/Vgate = 1,66667nF
extrapolated_Qgate(Q2) = 35nC
Cgate(Q2)=Qtotal/Vgate = 2,91667nF
Pdriver = Cgate*Vgate^2 * freq (300kHz)
Power disapation driver combined Q1 and Q2 = 0,072 + 0,126 = 0,198W
Power used to charge gates = 0,5*0,198W = 0,099W
thermal resistance driver=98degC/W
98*0,198 = 19,4 degrees C above ambient. (temperature rise in driver)
At one tau time the gates are at 63% enough to fully switch on. Switch off will take longer due to the low Vth spec. I go for three tau times.
Rgate+Rdriver=R
R(Q1) -> 1,5+3,0 = 4,5Ohm
R(Q2) -> 1,5+2,4 = 3,9Ohm
Q1(switch)time = 4,5*1,66667*10^-9 = 7,5nsec (switch off 22,5nsec)
Q2(switch)time = 3,9*2,91667*10^-9 = 11,4nsec (switch off 34,2nsec)
top MOSFET loss approximation: P(Q1)=Iout^2*Rds(on)*D+(0,5*Iout)*Vin*tsw*freq
bottom MOSFET loss approximation: P(Q2)=Iout^2*Rds(on)*(1-D)
Iout = 8A
D = 0,1 (1,2/12)
tsw = switch on + off time
P(Q1)= 0,46W
P(Q2)= 0,22W
Ploss(fet+drv) = P(Q1) + P(Q2) + P(drv) = 0,46 + 0,22 + 0,198 = 0,878W
AON6932 - €1,00
Q1_Rds(on) = 4,1mOhm
Q2_Rds(on) = 1,7mOhm
extrapolated_Qgate(Q1) = 19nC
Cgate(Q1)=Qtotal/Vgate = 1,58333nF
extrapolated_Qgate(Q2) = 64nC
Cgate(Q2)=Qtotal/Vgate = 5.33333nF
Pdriver = Cgate*Vgate^2 * freq (300kHz)
Power disapation driver combined Q1 and Q2 = 0,068 + 0,23 = 0,288W = P(drv)
Power used to charge gates = 0,5*0,288W = 0,144W
thermal resistance driver=98degC/W
98*0,288 = 28,2 degrees C above ambient. (temperature rise in driver)
At one tau time the gates are at 63% enough to fully switch on. Switch off will take longer due to the (very)low Vth spec. I go for three tau times.
Rgate+Rdriver=R
R(Q1) -> 1,5+3,0 = 4,5Ohm
R(Q2) -> 0,7+2,4 = 3,1Ohm
Q1(switch)time = 4,5*1,58333*10^-9 = 7,1nsec (switch off 21,4nsec)
Q2(switch)time = 3,1*5.33333*10^-9 = 16,5nsec (switch off 49,6nsec) <- (I don't like this long switchoff time)
top MOSFET loss approximation: P(Q1)=Iout^2*Rds(on)*D+(0,5*Iout)*Vin*tsw*freq
bottom MOSFET loss approximation: P(Q2)=Iout^2*Rds(on)*(1-D)
Iout = 8A
D = 0,1 (1,2/12)
tsw = switch on + off time
P(Q1)= 0,43W
P(Q2)= 0,18W
Ploss(fet+drv) = P(Q1) + P(Q2) + P(drv) = 0,43 + 0,18 + 0,288 = 0,898W
Conclusion: I pick the AON6973A. It's cheaper and at 8A output it results in a more efficient solution.
Note: Iout is squared in those formullae, a calculation for a somewhat higher current would tip the scales the other way.
Inductor selectionA pretty expensive part, but worth it if done right.
The standard way to pick one is to chose a ripple current you are willing to tolerate. I will tolerate a 30 to 40% ripple current.
That is pretty high, but in this case the application constantly uses a pretty high current, so low current efficiency is not that important. This does require a larger output capacitance.
L=(Vout*(Vin-Vout))/(Vin*freq*ripple_%*Iout(max))
(1,2*(12-1,2))/(12*300000*8*0,3) = 1,5uH (for 40% -> 1,125uH)
Chosen: Epcos B82559A0142A013 1,4uH 1,5mOhm 22A(Isat) €2,50 ~ €3,00
Ilpp = (1,2*(12-1,2))/(12*300000*(1,4*10^-6)) = 2,6A
Ilpeak = 8 + (0,5*2,6) = 9,3A
Il(RMS) = sqrt(Iout^2+(Ilpp^2)/12) = 8,03A
Worse case inductor temperature is, I guess 60degC or so. (guesswork!)
Rwire = 1,5mOhm * (1+0,0042*(60deg-20deg)) = 1,75mOhm
Pinductor(cu) = 8,03^2 * 1,75m = 0,113W
Conclusion: The inductor wire resistance is the biggest loss factor in the inductor at higher currents. Small loss compared to the mosfets and their driver.
Output capacitor selectionThere is only 1,2V at the output, so very low voltag capacitors can be chosen.
maximum ESR? It's primary cause of voltage ripple by absorbing the inductor peak to peak current.
Lets go for 24mV p-p
Ilripple (pp) = 2,6A
ESR<0,024/2,6 = 9,23mOhm (we'll manage)
I'll go for 2,5V nichicon caps, they have low ESR, they are cheap and next to that some small X5R caps to do the high frequency stuff.
Part chosen: Nichicon RHA0E821MCN1GS 2,5V 820uF 8mOhm 4,5AIrms €0,84
For high frequency 2x 0805 X5R 6,3V 22uF Murata GRM21BR60J226ME39L €0,38 (€0,76)
For really high freq spikes 1x 0306(reverse geometry) X5R 6,3V 4,7uF TaiyoJuden JWK107BJ475MV-T €0,53
Total = €2,13
Vout ripple(pp) = sqrt((2,6/((820*10^-6)*8*300000))^2 + (2,6*0,008)^2) = 20,8mV(pp)
How does this act during a load step? I would like a maximum voltage change of 50mV at a load step of 8A.
Estimate calculation: Cout(min)=(Istep^2*L)/(2*Vout*Vchange)= 747uF (we are allready over this)
The small inductance reduces the capacitance need for transient supression.
Icout(rms) = 2,6/sqrt(12) = 0,75A (way below the allowed 4,5A)
Pdiss(cout) = 0,75^2 * 0,008 = 0,0045W (negligible compared to the rest)
Input capacitor selectionHas to be able to handle the input voltage, load steps on the output. Reduce ripple on the 12V line.
Estimate for the required RMS current of the input capacitor.
Iincap(rms)=(Iout/Vin)*sqrt(Vout*(Vin-Vout))
(8/12)*sqrt(1,2*(12-1,2))=2,4A = Iincap(rms)
Minimum capcacitance for a certain ripple: (I chose 25mV)
Cin(min)=Iout*(D*(1-D)/(Vpp*freq))
8*(0,1*(1-0,1)/(0,025*300000)) = 96uF (seems a bit low)
Now take a formulla which factors in the esr with that ripple requirement.
I chose a 150uF 22mOhm capacitor to calculate (first with two, then three in parallel)
Vpp(esr)=esr*(Iout+(1/(2*freq*L))*D*(Vin-Vout)) ->102mV(x2cap) -> 68mV(x3cap)
Now for capcitance there are two formullas to do.
if 1<(Vout^2)/(2*freq*L*Iout-D*(Vin-Vout)) solve: Vpp(cap)=(1/(8*L))*((Vin-Vout)/(Cin*(Vin^2)))*(2*L*Iout+(Vout/freq))^2
if 1>(Vout^2)/(2*freq*L*Iout-D*(Vin-Vout)) solve: Vpp(cap)=(Iout*Vout*(Vin-Vout))/(freq*Cin*(Vin^2))
The first equation was smaller than 1 (=0,255)
So I solved Vpp(cap)=(Iout*Vout*(Vin-Vout))/(freq*Cin*(Vin^2)) -> 8mV(x2cap) -> 5,3mV(x3cap)
It is clear that the ESR has the largest influence on the input ripple.
Parts chosen: 3x Nichicon RHA1C151MCN1GS 16V 150uF 22mOhm €0,90 (€2,70)
For high frequency: 1210 X7R 25V 22uF TaiyoJuden TMK325B7226MM-TR (€0,85)
TaiyoJuden TMK107ABJ225KA-T (€0,23)
Total = €3,78
Do note that these 450uF*12=5400uF are all attached to the PSU and the supplier does not specify a maximum startup capacitance.
But it is a fairly modern PSU, perhaps it will be no issue.
Power loss input cap:
Pdiss(cin)=Iincap(rms)^2 *esr -> 2,4^2*0,0073 = 0,042W
Estimated efficiency at 8A output current: (worst case)Ploss(total)=Pdiss(cin)+Pdiss(cout)+Pinductor(cu)+Ploss(fet+drv) = 0,042+0,0045+0,113+0,878 = 1,038W
Pload = 1,2V*8A = 9,6W
Pinput = Ploss(total)+Pload = 1,038+9,6 = 10,638W
efficiëncy = Pload/Pinput = 9,6/10,638 =
90,24% (not bad)
Room for improvement? Most losses are located at the mosfets and the driver. Cost spent there might be most effective.
Solution cost:
€12,17 (pretty expensive, but worth it, I hope)
Overcurrent protectionRocset is attached to the lower drive output. The value is measured by the controller at startup.
It will trip at a set peak inductor current.
Ipeak=(2*Iocset*Rocset)/Rds(on)
Iocset(min) = 19,5uA
Rds(on)@125C = 5,3mOhm
Ipeak = 10A (safe value)
Rocset = (Rds(on)*Ipeak)/(2*Iocset) = 1359Ohm (rounded to practical value, 1k5 1%)
Output voltage set (feedback)The output voltage is twice the Vref, so Rs and Ro are equal.
Rs is the top resistor
Ro is the bottom resistor
Vref = 0,6V
Vout = 1,2V
Ro = (Rs*0,6V)/(Vout-0,6V)
I chose 3,3KOhm for both
Feedback compensation Our controller has to respond quickly to transient loads, but should at the same time be immune to the switching ripple and should be slower than the output filter to prevent all kinds of bad mojo. ie. phase margin above 45deg at 0dB to be safe.
http://s13.postimg.org/zf2t2dth3/smps_feedback_comp.jpgThat is how it looks like, now to determin the component values. I'll just follow the datasheet guidelines as they probably know their part best. I still should try to simulate the bode(gain/phase) plot in matlab or whatever.
3db freq lc filter 1/(2*pi*sqrt(1,4uH*820uF)) = 4,7kHz =Flc
3db freq cap+esr filter 1/(2*pi*820uF*8mOhm) = 24,2kHz = Fce
R1 = 3,3kOhm
F0 = 60000Hz (0,2*300000) (safe distance from the switching frequency)
d(max) = 1 (duty cycle in this convertor can go to 100%)
Vosc = 1,5V (typical value)
R2 = (Vosc*R1*F0)/(d(max)*Vin*Flc) = 5266Ohm -> 5230Ohm is the closest E96 value
I'm going to place the zero (Fz1) a bit lower than usual because of the high Fce/Flc factor. (quality factor)
C1=1/(2*pi*R2*0,25*Flc)= 25,9nF -> 22nF ( common value )
The Fp1 pole should lie at Fce.
C2=C1/((2*pi*R2*C1*Fce)-1)= 1,33nF -> 1,3nF is a regular value
Place zero Fz2 at Flc
R3=R1/((Fsw/Flc)-1) = 52,5Ohm -> 52,3Ohm chosen
Place pole Fp2 at between 0,5 to 1,0 the Fsw. I'll try first at 0,7 and pick the closest real value and check where we ended up.
C3=1/(2*pi*R3*0,7*Fsw) = 14,5nF -> 15nF is normal. (we ended up at about 0,68*Fsw)
So I simulated that in the webbased software of the supplier of the controller.
First theoretical:
http://s15.postimg.org/72gwz718r/Loop_response_theoretical.jpgLooks fine, the margin is nearly 60degrees.
Now a simulation of the whole system:
http://s12.postimg.org/ips1gp90d/loop_response_simulation.jpgA somewhat higher 0dB crossover at 74KHz and a lower margin at 54 degrees.
I'm satisfied with that. This system will be able to handle extreme transients. And all that for sacrificing some ripple suppression. Worth it.
tl;dr this smps is awesome