New problem.
I've got both my X6500 boards up and "running", but while one of them (-d 1) is returning golden nonces every few jobs, the other one has been running for ~10 minutes without a single golden nonce.
Is this expected? What could the problem be?
Edit: Had a problem with my jury-rigged power supplies and had to reload -d 1, and when I came back it was spinning its wheels too.
Topic: X6500 Custom FPGA Miner - page 46. (Read 220050 times)
I'm having some trouble as well.
Running program.py gives this error:I ran a quick nm command on the libftd2xx.so I downloaded from the site you indicated, and sure enough, there's no such symbol in the library.
I'm on 32-bit Linux, if it matters.
Edit: Bar that; solution found. Turns out there's four functions whose metadata you commented out in the modified python libraries, but you forgot to comment out the functions themselves. So it tried to link to them, and.... bang!
Running program.py gives this error:
Code:
Traceback (most recent call last):
File "program.py", line 23, in
from ft232r import FT232R, FT232R_PortList
File "/home/[redacted]/x6500-miner/ft232r.py", line 22, in
import d2xx
File "/usr/lib/python2.7/site-packages/d2xx/__init__.py", line 24, in
from _d2xx import *
ImportError: /usr/lib/python2.7/site-packages/d2xx/_d2xx.so: undefined symbol: FT_CyclePort
I'm on 32-bit Linux, if it matters.
Edit: Bar that; solution found. Turns out there's four functions whose metadata you commented out in the modified python libraries, but you forgot to comment out the functions themselves. So it tried to link to them, and.... bang!
I'm seeing:
This seems to be due to a flaky usb hub. Code:
...
_d2xx.Error: (4, 'IO error')
Now getting:
Code:
(FPGA0) Golden nonce found
IO Error!
(FPGA0) rejected 72ba42c7L
(FGPA0) Connecting...
(FGPA0) accepted 72ba42c7L
Shad, could you try the latest from github? There may have been a fix for your problem in the last couple weeks (after the v0.1 release).
To everyone with software issues: I have been traveling for the past week but am returning home today. I'll look into each of those issues as soon as possible (on the plane if there's wifi). Until then, please post as much info as you can (OS, etc). Thanks!
fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.
You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.
fpgaminer, would that work?
You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.
fpgaminer, would that work?
Hm, doesn't seem fpgaminer is reading this...
Hi Molecular, yes it does seem like this is the easiest way to maintain support for the X5000, although you'd have to spend a little bit for more hardware.
fpgaminer said he would test this out with his X5000, but I'm not sure he's had time to yet. It is a very slim chance that it won't work, though, so a test is really only a formality. How about I buy that cable, send it to you, and if it works you pay me for it? If it doesn't, keep the cable for a future project and we'll look for another solution.
Awesome offer! Of course I'll go for it. I'll PM you my snail mail address. Thanks in advance.
so its 9:00
i checked my pool stats before going to work and the last block payout is "none"
anyone else with having those kind of troubles? 3rd time for me
i checked my pool stats before going to work and the last block payout is "none"
Quote
[2011-12-21 04:21:47] (FPGA0) Golden nonce found
[2011-12-21 04:21:47] (FPGA0) accepted 89bb0b10L
[2011-12-21 04:22:02] (FPGA1) Job data loaded in 0.063 seconds
[2011-12-21 04:22:03] (FPGA0) Job data loaded in 0.047 seconds
[2011-12-21 04:22:12] (FPGA1) Golden nonce found
[2011-12-21 04:22:12] (FPGA1) accepted 515487ebL
[0 kH/s] [0: 2607/316 (10.81%)] [1: 2560/314 (10.93%)] [1918 min] AH00WIX5
[2011-12-21 04:21:47] (FPGA0) accepted 89bb0b10L
[2011-12-21 04:22:02] (FPGA1) Job data loaded in 0.063 seconds
[2011-12-21 04:22:03] (FPGA0) Job data loaded in 0.047 seconds
[2011-12-21 04:22:12] (FPGA1) Golden nonce found
[2011-12-21 04:22:12] (FPGA1) accepted 515487ebL
[0 kH/s] [0: 2607/316 (10.81%)] [1: 2560/314 (10.93%)] [1918 min] AH00WIX5
anyone else with having those kind of troubles? 3rd time for me
What is the warranty on these boards? Assuming the difficulty and exchange rate stay reasonable constant, it'll take about 2 years to break even, assuming the boards run that long.
I'm seeing:
which doesn't sound good.
Any ideas?
Code:
Saved pre-processed bitstream in 7.531000 seconds
Beginning programming...Programming both FPGAs...
Completed: 0.0% [33 kB/s] [2m7s remaining]Traceback (most recent call last):
File "program.py", line 201, in (module)
programBitstream(ft232r, jtag, settings.chain, processed_bitstream)
File "program.py", line 80, in programBitstream
jtag.load_bitstream(processed_bitstream, logger.updateProgress)
File "C:\x6500\jtag.py", line 284, in load_bitstream
wrote = self.ft232r.handle.write(chunk)
_d2xx.Error: (4, 'IO error')
Any ideas?
Sorry that took so long to pre-process. If you pre-process it on one machine, you can safely move that pre-processed file to another machine, so you might want to do the pre-processing on a faster computer next time then move it to your tablet.
this was only an info for new X6500 users, because i was worried while waiting 
2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker
as written on fpgamining.com its -u for pool and -w for user/worker
Where did you see this? I'd like to make sure everything is consistent, but everywhere I look it says -u and -w. Thanks.
start mine.py without parameters and you will see it
ERROR: URL not specified!
Usage: mine.py [-d
today i had to restart the miner-software the second time because of doing nothing?
this happens after a day or so, speed brake down to 0khs/sec
if it happens again i will send you the screenoutput, no errors or something else
i hope it has nothing to do with running phyton 2.6.6, as 2.6.7 is recommended
fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.
You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.
fpgaminer, would that work?
You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.
fpgaminer, would that work?
Hm, doesn't seem fpgaminer is reading this...
Hi Molecular, yes it does seem like this is the easiest way to maintain support for the X5000, although you'd have to spend a little bit for more hardware.
fpgaminer said he would test this out with his X5000, but I'm not sure he's had time to yet. It is a very slim chance that it won't work, though, so a test is really only a formality. How about I buy that cable, send it to you, and if it works you pay me for it? If it doesn't, keep the cable for a future project and we'll look for another solution.
By the way, I know that fpgaminer is also trying to up the clock rate on the original X5000 bitstream, but don't know how that's going.
winXP
Tablet PC Edition 2005
SP3
fizzisist-x6500-miner-02b13e3 with phyton 2.6.6 because 2.6.7 is only source and i have no windows compile tools installed
Intel Celeron M 900Mhz 1GB-Ram
1.) program.py, it tooks only 1 minute, but first time it took me 12minutes to pre-process bitstream, but this is only at first time run because its stored on the hdd
Tablet PC Edition 2005
SP3
fizzisist-x6500-miner-02b13e3 with phyton 2.6.6 because 2.6.7 is only source and i have no windows compile tools installed
Intel Celeron M 900Mhz 1GB-Ram
1.) program.py, it tooks only 1 minute, but first time it took me 12minutes to pre-process bitstream, but this is only at first time run because its stored on the hdd
Sorry that took so long to pre-process. If you pre-process it on one machine, you can safely move that pre-processed file to another machine, so you might want to do the pre-processing on a faster computer next time then move it to your tablet.
2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker
as written on fpgamining.com its -u for pool and -w for user/worker
Where did you see this? I'd like to make sure everything is consistent, but everywhere I look it says -u and -w. Thanks.
if you get this kind of errors your pool-server-url may be false, in my case wrong port
i would change that error to "IOError! - pool communication problem" or something
i would change that error to "IOError! - pool communication problem" or something
Quote
[2011-12-16 19:09:23] (FPGA0) Connecting...
[2011-12-16 19:09:23] (FPGA0) Clearing queue...
[2011-12-16 19:09:23] (FPGA1) Connecting...
[2011-12-16 19:09:24] (FPGA0) Queue cleared.
[2011-12-16 19:09:24] (FPGA1) Clearing queue...
[2011-12-16 19:09:26] (FPGA1) Queue cleared.
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:29] (FPGA0) Connecting...
[2011-12-16 19:09:29] (FPGA1) Connecting...
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] (FPGA1) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA0) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA1) Connecting...
[2011-12-16 19:09:34] (FPGA0) Connecting...
[2011-12-16 19:09:23] (FPGA0) Clearing queue...
[2011-12-16 19:09:23] (FPGA1) Connecting...
[2011-12-16 19:09:24] (FPGA0) Queue cleared.
[2011-12-16 19:09:24] (FPGA1) Clearing queue...
[2011-12-16 19:09:26] (FPGA1) Queue cleared.
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:29] (FPGA0) Connecting...
[2011-12-16 19:09:29] (FPGA1) Connecting...
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] (FPGA1) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA0) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA1) Connecting...
[2011-12-16 19:09:34] (FPGA0) Connecting...
Nice find, I'll look into that. We definitely need help improving stuff like that.
i am running on 133mhz 
not so hot now, but its cooled by a ventilator
how high is the limit for passiv cooling?
not so hot now, but its cooled by a ventilator
how high is the limit for passiv cooling?
Awesome, and congrats! Thanks for all your work and your report. As for passive cooling, so far no one knows exactly. I'll do some testing soon, but anyone who tries it please let us know how it goes and what clock rate you used.
No code improvements for higher hashrate yet?
Sorry for the very late reply. Unfortunately, no improvements yet. Once these boards are finally on their way out to customers, we expect to be able to devote a lot more time to that work.
When updating software, can you keep in mind your first customers that have x5000?
Yes, absolutely. Unfortunately, I really don't know much about the X5000, because it was before my time. We need fpgaminer's help, but he's mostly MIA lately because he is swamped with work and moving to a new apartment right now. Hopefully he will be able to work on this stuff soon.
I do know that if you could switch from the Xilinx platform cable to an FT232R breakout board, the hardware and software interface would be identical to the X6500, so all code would be completely compatible. This would also eliminate the need for ISE.
Actually, this cable soldered to the correct connector would probably be perfect. If you were willing to pay for the cable, I'd be happy to solder it up and send it to you. At that point, I think you would just plug it in and run the X6500 software (with the X6500 bitstream) and you'd be off and running.
fpgaminer, can you confirm that my idea makes sense? Do you have other ideas for how to maintain support for the X5000?
fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.
You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.
fpgaminer, would that work?
Hm, doesn't seem fpgaminer is reading this...
Hi Molecular, yes it does seem like this is the easiest way to maintain support for the X5000, although you'd have to spend a little bit for more hardware.
No code improvements for higher hashrate yet?
Sorry for the very late reply. Unfortunately, no improvements yet. Once these boards are finally on their way out to customers, we expect to be able to devote a lot more time to that work.
When updating software, can you keep in mind your first customers that have x5000?
Yes, absolutely. Unfortunately, I really don't know much about the X5000, because it was before my time. We need fpgaminer's help, but he's mostly MIA lately because he is swamped with work and moving to a new apartment right now. Hopefully he will be able to work on this stuff soon.
I do know that if you could switch from the Xilinx platform cable to an FT232R breakout board, the hardware and software interface would be identical to the X6500, so all code would be completely compatible. This would also eliminate the need for ISE.
Actually, this cable soldered to the correct connector would probably be perfect. If you were willing to pay for the cable, I'd be happy to solder it up and send it to you. At that point, I think you would just plug it in and run the X6500 software (with the X6500 bitstream) and you'd be off and running.
fpgaminer, can you confirm that my idea makes sense? Do you have other ideas for how to maintain support for the X5000?
fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.
You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.
fpgaminer, would that work?
Hm, doesn't seem fpgaminer is reading this...
after some testing the client said "connected to server" and then nothing,
retry => same issue
after new programming with bitstream it worked again
no major problem, just an info
and i have to say
nice work, nice product!!!
retry => same issue
after new programming with bitstream it worked again
no major problem, just an info
and i have to say
nice work, nice product!!!
winXP
Tablet PC Edition 2005
SP3
fizzisist-x6500-miner-02b13e3 with phyton 2.6.6 because 2.6.7 is only source and i have no windows compile tools installed
Intel Celeron M 900Mhz 1GB-Ram
1.) program.py, it tooks only 1 minute, but first time it took me 12minutes to pre-process bitstream, but this is only at first time run because its stored on the hdd
2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker
if you get this kind of errors your pool-server-url may be false, in my case wrong port
i would change that error to "IOError! - pool communication problem" or something
i am running on 133mhz
not so hot now, but its cooled by a ventilator
how high is the limit for passiv cooling?
Tablet PC Edition 2005
SP3
fizzisist-x6500-miner-02b13e3 with phyton 2.6.6 because 2.6.7 is only source and i have no windows compile tools installed
Intel Celeron M 900Mhz 1GB-Ram
1.) program.py, it tooks only 1 minute, but first time it took me 12minutes to pre-process bitstream, but this is only at first time run because its stored on the hdd
2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker
if you get this kind of errors your pool-server-url may be false, in my case wrong port
i would change that error to "IOError! - pool communication problem" or something
Quote
[2011-12-16 19:09:23] (FPGA0) Connecting...
[2011-12-16 19:09:23] (FPGA0) Clearing queue...
[2011-12-16 19:09:23] (FPGA1) Connecting...
[2011-12-16 19:09:24] (FPGA0) Queue cleared.
[2011-12-16 19:09:24] (FPGA1) Clearing queue...
[2011-12-16 19:09:26] (FPGA1) Queue cleared.
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:29] (FPGA0) Connecting...
[2011-12-16 19:09:29] (FPGA1) Connecting...
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] (FPGA1) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA0) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA1) Connecting...
[2011-12-16 19:09:34] (FPGA0) Connecting...
[2011-12-16 19:09:23] (FPGA0) Clearing queue...
[2011-12-16 19:09:23] (FPGA1) Connecting...
[2011-12-16 19:09:24] (FPGA0) Queue cleared.
[2011-12-16 19:09:24] (FPGA1) Clearing queue...
[2011-12-16 19:09:26] (FPGA1) Queue cleared.
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:29] (FPGA0) Connecting...
[2011-12-16 19:09:29] (FPGA1) Connecting...
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] (FPGA1) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA0) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA1) Connecting...
[2011-12-16 19:09:34] (FPGA0) Connecting...
i am running on 133mhz
not so hot now, but its cooled by a ventilator
how high is the limit for passiv cooling?
Hm my postal service seems to have gone for holidays alreday. Nothing has arrived here yet.
Finally got started mining with mine and so far it's nice!!!
Glad to hear it! And thanks for being the first independent tester! Please let us know how everything goes.
Just to confirm, something like this should work if I prefer external power??
http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_2123266_-1
Or will cablesaurus have a better deal on something soon?
http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_2123266_-1
Or will cablesaurus have a better deal on something soon?
That looks like a nice find, but there is some conflicting information in its description. The product name says 2.1x5.5mm connector, but the specs below say 2.5x5.5mm. In reality, that 0.4 mm should not make much difference, but it's much safer to use one that exactly matches the connector on the board (which has a 2.1 mm center pin).
Cablesaurus is getting power supplies in stock, but I want to test one out before we give it the official recommendation. That should be getting to me next week. Not sure how long it will be before Cablesaurus has them for sale, though.
Just to confirm, something like this should work if I prefer external power??
http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_2123266_-1
Or will cablesaurus have a better deal on something soon?
http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_2123266_-1
Or will cablesaurus have a better deal on something soon?
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