So, let's explain how an FPGA works, first.
You have logic gates, (which compute logical functions like 'and' 'or' etc) Those logic gates can be connected to other gates by using transistors to switch on and off wires connecting them. Those configuration transistors take up a ton of space on the die.
an eASIC 'nextreme' ASIC works like an FPGA, except they get rid of those transistors that do the linking and replace them wires that directly connect the logic units. That saves a ton of space because you need far fewer transistors to do the same thing and it's easier to design because you just take a working FPGA and 'convert' it fairly cheaply.
Now, a full custom ASIC is designed by creating images of layers. You start with the silicon layers with N and P doped silicon which form transistors. You literally have a vector graphics file (called a usually a
GDSII file) that indicates where you want N-type silicon and where you want P-type silicon.
then, on top of that you have multiple images for multiple layers of metal and glass (silicon dioxide) The metal conducts electricity, and the glass is an insulator. These layers form wires that connect the transistors together. If you go full custom you can do things like create transistors of different shapes and sizes that can carry different currents and operate have different switching characteristics. This gives you the highest performance possible.
Standard cell is similar to full custom, but you're using libraries of 'images' to create your circuit, rather then creating the images 'pixel by pixel' (They're actually vector files, but whatever). So you'll have a library for an adder, or an XOR gate, shiftier, and so on - the components you need to do SHA-256 (all you need is XOR, shift, rotate and 32-bit addition). Full custom might give you slightly better performance because you can do more 'analog' optimizations.
The biggest difference between 'nextreme' style and standardcell/custom ASICs are the fact that you can have more 'fan-in'. So you can do things like AND(a b c d e f g) Where as with only two inputs per gate you'd need to do multiple nested gates in order to compare all of those variables. I'm not sure what the max fan-in is on nextreme chips (I'm sure it's under NDA), but there are some places where having larger fan in would help, like using more lanes in your
ripple carry adders.
Many thanks! That's a pretty vivid explanation.
The press release was spread by
www.businesswire.com:
https://www.google.com/search?q=VMC+Uses+eASICAnd boardmembers:
I think there is a typo either in the press release or on the VMC website. 24.756 TH/s != 24.576 TH/s.
