Propably becuse you are only one that recived chips. Great work by the way...
Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 42. (Read 176727 times)
June 26, 2013, 05:49:05 AM
June 26, 2013, 05:43:38 AM
Layout for 'bitfury H-CARD', the low cost miner board,
has been accepted and is now inproduction:
http://imgur.com/IWBq5Ct
intron
has been accepted and is now inproduction:
http://imgur.com/IWBq5Ct
intron
Hi intron, can you clarify in which way you are involved with bitfury? Is this the official board bitfury/metabank yis going to use or is it just a prototype board? I didnt saw thr information, am i blind or simply stupid?
I'm just one of the alfa-testers. bitfury asked me to post
the progress I make, so that's what I'm doing here in this
thread. Looks like I'm still the only one doing so:)
intron
June 26, 2013, 04:34:34 AM
Layout for 'bitfury H-CARD', the low cost miner board,
has been accepted and is now inproduction:
http://imgur.com/IWBq5Ct
intron
has been accepted and is now inproduction:
http://imgur.com/IWBq5Ct
intron
Hi intron, can you clarify in which way you are involved with bitfury? Is this the official board bitfury/metabank yis going to use or is it just a prototype board? I didnt saw thr information, am i blind or simply stupid?
June 26, 2013, 03:55:27 AM
great news!
June 26, 2013, 03:48:09 AM
Layout for 'bitfury H-CARD', the low cost miner board,
has been accepted and is now in production:
intron
has been accepted and is now in production:
intron
June 25, 2013, 12:37:34 PM
I will test chips, PM me please... 
June 25, 2013, 11:45:26 AM
Been listening to this for hours on end:
https://www.youtube.com/watch?v=sbA7rrnbe6E
Helped me thru the night:)
Layout of bitfury H-CARD (the low-cost 16 ASIC hash card)
nears completion.
intron
https://www.youtube.com/watch?v=sbA7rrnbe6E
Helped me thru the night:)
Layout of bitfury H-CARD (the low-cost 16 ASIC hash card)
nears completion.
intron
I assume you have had a heavy dose of Fela as well. Saved me many a time.
June 25, 2013, 10:29:02 AM
Been listening to this for hours on end:
https://www.youtube.com/watch?v=sbA7rrnbe6E
Helped me thru the night:)
Layout of bitfury H-CARD (the low-cost 16 ASIC hash card)
nears completion.
intron
https://www.youtube.com/watch?v=sbA7rrnbe6E
Helped me thru the night:)
Layout of bitfury H-CARD (the low-cost 16 ASIC hash card)
nears completion.
intron
June 25, 2013, 07:11:50 AM
Struth, this is moving along fast. KNCminer watch out.
June 25, 2013, 03:19:54 AM
I'm interested in 16-20 chips for testing and R&D here in Canada.
Would love a USB single or double board made up. Maybe I can reverse engineer one off the s-hash!
What do you need for shipping costs?
Would love a USB single or double board made up. Maybe I can reverse engineer one off the s-hash!
What do you need for shipping costs?
June 25, 2013, 03:03:10 AM
really nice to see how the work boils, and everything is going in the right direction 
+1
June 24, 2013, 11:59:29 PM
Development mining board 'bitfury S-HASH' is underway:
From this the low-cost mining boards will be derived.
We get it working hopefully soon and try to learn from it.
intron
From this the low-cost mining boards will be derived.
We get it working hopefully soon and try to learn from it.
intron
June 24, 2013, 05:53:42 PM
really nice to see how the work boils, and everything is going in the right direction
June 24, 2013, 05:13:19 PM
VDD => lets's forget the IOREF line.
Nice. It's in the schematic already:)
June 24, 2013, 05:11:08 PM
Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
Yes. This is why IOREF pin is there (near VDD
. If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.So what to do on the mining board: connect IOREF to Vcore or connect IOREF to IOVDD/2?
intron
VDD => lets's forget the IOREF line.
June 24, 2013, 05:07:39 PM
Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
Yes. This is why IOREF pin is there (near VDD
. If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.So what to do on the mining board: connect IOREF to Vcore or connect IOREF to IOVDD/2?
intron
June 24, 2013, 03:49:19 PM
Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
http://imgur.com/QZYoGDQ
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
Yes. This is why IOREF pin is there (near VDD
. If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences. June 24, 2013, 03:38:45 PM
Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.
Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.
Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.
intron
June 24, 2013, 02:07:16 PM
Latest test was done to maximize performance, while
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.
Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.
Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.
Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.
With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.
http://imgur.com/g7UTw6V
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.
Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.
Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.
Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.
With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.
http://imgur.com/g7UTw6V
Great results! Thanks! Hopefully tomorrow Leszek will send more chips, and we'll know more data!
But take care of power noise.
We still need to find out how to chain the SPI bus. The
bitfury S-HASH mining board layout is ready, waiting for
funds to get it etched. Leszek is working on this. When
this board arrives we finally can put 16 bitfury's to work
simultaneously:)
intron
June 24, 2013, 02:02:53 PM
Latest test was done to maximize performance, while
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.
Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.
Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.
Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.
With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.
http://imgur.com/g7UTw6V
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.
Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.
Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.
Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.
With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.
http://imgur.com/g7UTw6V
Great results! Thanks! Hopefully tomorrow Leszek will send more chips, and we'll know more data!
But take care of power noise.
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