Can someone translate what bitfury said in his long post?
OK, I'll try...
Bitfury did just a short burst tests (lasting at most few seconds) of his chip at various voltages and various speeds. He still need to test it under a continuous load and at various temperatures.
Now I switch to explaining what he didn't do. He didn't use any "standard cell", "library" or other purely digital logic EDA tools, which were thus far used by all other competitors. They used unrolled pipeline designs and their simulations were very inaccurate-purely digital. Due to the very approximate simulation and high toggle rate of the flip-flops in SHA-256 the real power used by competitor chips was significantly higher than the simulated power usage.
Now I switch back to what he did do. After completing the initial digital logic design he had switched to a full-custom design process: he no longer designed at the gate or flip-flop level but at the individual transistor level. He no longer dealt with zeros and ones but with volts and amperes. He had used a very precise analog models of the transistors from the foundry and used analog circuit simulators: SPICE and/or BSIM. This was possible without multimillion budget because he didn't unroll the hashing kernels but kept them rolled and replicated them several hundred times over the area of the chip. The additional benefit was that his power simulations were very accurate: the simulation error margins were lower than the wafer manufacture process error margins.
One of the goals he had choosen for his chip was to have them work with rather wide ranges of the supply voltages, in particular with uncommonly low voltages. To achieve that he had paid extreme attention to minimizing the switching noise both inside the chip and on the chip pins. In particular despite of the relatively low clock speed (100MHz or low hundreds MHz) the I/O design methodology was the one used for GHz signals (or high hundreds of MHz).
Because of the above goals his chip isn't really plug-and-play for designers used to deal with typical digital logic design workflows and tools. To get all thats possible out of his chip requires familiarity with analog and mixed signal design. In particular it requires familiarity with transmission line modeling to design the best PCB with a large quantity of his chips. His goal is to publish
http://en.wikipedia.org/wiki/Scattering_parameters required to accurately model the I/O terminals of his chip.
He probably already has a good idea of what those S-parameters are from the high accuracy simulations using SPICE/BSIM. But possibly he either can't (because of NDA with the foundry) or doesn't want (for competitive advantage reasons) release his internal models and their parameters. Additionally, the S-parameters are affected by the quality of packaging of the chip and there is no real substitute for making the actual measurements, for which he plans to use devices made by
http://www.signalhound.com/ .
Obviously, I'm not bitfury, and the above is just my educated guess.