Update 14/4/15:Thank you all for waiting so patiently, today we'd like to announce some long awaited specifications for the SF3301!
The SF3301 fully utilizes the advantages of the FD-SOI technology. With increased forward body bias the chip is operational at lower voltages while maintaining a higher frequency. The chip boasts impressive power efficiency while affording high hash power, allowing for much lower wastage per hash. The ASIC’s lowest working voltage is 0.45V, with lowest BTC efficiency at 0.19J/GH, and lowest LTC efficiency at 1.75J/MH. In current market conditions compared to other mining technology, dual-algorithm capabilities can provide a clear advantage.
After strenuous testing of the SF3301, we reached hashrates of 152GH/s for SHA-256 and 3.17MH/s for Scrypt.
This month we will also be releasing a number of documents for the SF3301 as open source including the ASIC Development Board designs.
Next month we will release some design specifications for our debut miner.
Additionally in the near future SFARDS will be selling ASIC development boards and sample chips, making the SF3301 accessible to developers who wish to customize and build their own hardware. SFARDS welcomes any and all developers and communities to build upon our technology and contribute to the mining ecosystem.
Please contact
[email protected] for more information.