[ANN][BLC] Blakecoin Blake-256 for GPU/FPGA With Merged Mined Pools Stable Net - page 178.

atavacron

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The definition of insanity is doing the same thing

Quote from: kramble on October 29, 2013, 09:45:42 AM

Quote from: atavacron on October 29, 2013, 09:31:36 AM

Darn. The new build doesn't seem to work...the FPGAs think that they are running @ 1073741823MHz. I also tried forcing the overclock to 60MHz but it didn't change anything.

Darn indeed. 1073741823 is 3FFFFFFF so I'm guessing that the problem is in the JTAG interface (just like the 150MHz version that was reporting 26MHz for the clock frequency instead of 50Mhz). It would be useful to know if the "working" build is reporting the correct clock frequency on readback (and what the max working freq is). I'll do that 100Mhz build anyway as it may be some weird effect of the initial DCM clock which is breaking it so it may just work.

So it looks like I'm going to have to debug the JTAG on my lancelot after all. That's going to be quite challenging (I'll need to swap out the ft232 driver and write a custom one to drive the Xilinx platform cable, luckily its a parallel port so no reverse engineering needed). This is going to take all week I expect. In the meantime I'll tinker with the code a bit more if you don't mind doing an occasional test run.

Sure.

It looks like the max freq using "X6500-Robust-v02-fmax-100MHz.bit" is 63MHz. If I try 64MHz the reported freq is 4294967295MHz and the miner sits idle.

63MHz

Code:

64MHz

Code:

python mine.py -d 0 -u 127.0.0.1:8772 -w --verbose --overclock 64

2013-10-29 10:53:19 | Device 0 opened (A5VNUHQI)
2013-10-29 10:53:19 | Discovering FPGA 0...
2013-10-29 10:53:19 | 0: Waking up...
2013-10-29 10:53:20 | Found 1 device:
2013-10-29 10:53:20 | FPGA0: Spartan 6 LX150 - Firmware: rev 4, build 2
2013-10-29 10:53:20 | Discovering FPGA 1...
2013-10-29 10:53:20 | 1: Waking up...
2013-10-29 10:53:20 | Found 1 device:
2013-10-29 10:53:20 | FPGA1: Spartan 6 LX150 - Firmware: rev 4, build 2
2013-10-29 10:53:20 | Connected to 2 FPGAs
2013-10-29 10:53:20 | FPGA 0 is running at 4294967295MHz
2013-10-29 10:53:20 | FPGA 1 is running at 4294967295MHz
2013-10-29 10:53:20 | Connecting to server...
2013-10-29 10:53:20 | Connected to server
2013-10-29 10:53:20 | 0: Clearing queue...
2013-10-29 10:53:20 | 0: Queue cleared
2013-10-29 10:53:20 | 1: Clearing queue...
2013-10-29 10:53:20 | 1: Queue cleared
2013-10-29 10:53:20 | 0: Loading new job...
2013-10-29 10:53:20 | 0: Writing job...
0 kH/s | 0: 0/0/0 0.0%/0.0% | 1: 0/0/0 0.0%/0.0% | 0s | A5VNUHQImidstatehex= f9983e6cb09838fafe641039c362c67c99975071a4d9ea0d941677b882ff8510
2013-10-29 10:53:20 | 0: Job data loaded in 0.032 seconds
2013-10-29 10:53:20 | 1: Loading new job...
2013-10-29 10:53:20 | 1: Writing job...
0 kH/s | 0: 0/0/0 0.0%/0.0% | 1: 0/0/0 0.0%/0.0% | 0s | A5VNUHQImidstatehex= 0e84ed3510722967eb1ffbef4935355cb1c23b8c1d228cea803b807db04d04b3
2013-10-29 10:53:20 | 1: Job data loaded in 0.033 seconds
2013-10-29 10:53:21 | Exiting...

kramble

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Activity: 384

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Quote from: atavacron on October 29, 2013, 09:31:36 AM

Darn. The new build doesn't seem to work...the FPGAs think that they are running @ 1073741823MHz. I also tried forcing the overclock to 60MHz but it didn't change anything.

Darn indeed. 1073741823 is 3FFFFFFF so I'm guessing that the problem is in the JTAG interface (just like the 150MHz version that was reporting 26MHz for the clock frequency instead of 50Mhz). It would be useful to know if the "working" build is reporting the correct clock frequency on readback (and what the max working freq is). I'll do that 100Mhz build anyway as it may be some weird effect of the initial DCM clock which is breaking it so it may just work.

So it looks like I'm going to have to debug the JTAG on my lancelot after all. That's going to be quite challenging (I'll need to swap out the ft232 driver and write a custom one to drive the Xilinx platform cable, luckily its a parallel port so no reverse engineering needed). This is going to take all week I expect. In the meantime I'll tinker with the code a bit more if you don't mind doing an occasional test run.

atavacron

full member

Activity: 224

Merit: 100

The definition of insanity is doing the same thing

Quote from: kramble on October 29, 2013, 09:02:12 AM

Quote from: atavacron on October 29, 2013, 08:52:40 AM

OK. I'm running overclock'd right now.

Wow, 7k diff.

Cheers. The new build is done (sometimes it can go quickly) ...

https://www.dropbox.com/s/77wg1smijyfpvx3/X6500-Robust-v03-2core-fmax-60MHz.bit

The timing report gives 71MHz as max speed, so in practice you may get 90-100MHz out of it (still well below the 200MHz for my current lancelot build, but its still somewhere around 400Mhash/s for the pair of devices). Just going to start off a 100Mhz build now (this will probably take much longer as its well above the 71MHz initial max, perhaps I'll just do a 80Mhz one first).

Let me know if the new build works (I may well have introduced some bugs with the multicore port).

Darn. The new build doesn't seem to work...the FPGAs think that they are running @ 1073741823MHz. I also tried forcing the overclock to 60MHz but it didn't change anything.

Code:

python mine.py -d 1 -u 127.0.0.1:8772 -w --verbose
2013-10-29 10:22:33 | Device 1 opened (A5VNV3JE)
2013-10-29 10:22:33 | Discovering FPGA 0...
2013-10-29 10:22:34 | 0: Waking up...
2013-10-29 10:22:34 | Found 1 device:
2013-10-29 10:22:34 | FPGA0: Spartan 6 LX150 - Firmware: rev 4, build 2
2013-10-29 10:22:34 | Discovering FPGA 1...
2013-10-29 10:22:34 | 1: Waking up...
2013-10-29 10:22:34 | Found 1 device:
2013-10-29 10:22:34 | FPGA1: Spartan 6 LX150 - Firmware: rev 4, build 2
2013-10-29 10:22:34 | Connected to 2 FPGAs
2013-10-29 10:22:34 | FPGA 0 is running at 1073741823MHz
2013-10-29 10:22:34 | FPGA 1 is running at 1073741823MHz
2013-10-29 10:22:34 | Connecting to server...
2013-10-29 10:22:34 | Connected to server
2013-10-29 10:22:34 | 0: Clearing queue...
2013-10-29 10:22:38 | Exiting...
Run Summary:
-------------
Device: 1
Serial: A5VNV3JE
Number of FPGAs: 2
Running time: 4s
Getwork interval: 20 secs
FPGA 0:
  Accepted: 0
  Rejected: 0 (0.00%)
  Invalid: 0 (0.00%)
  Hashrate (all nonces): 0 kH/s
  Hashrate (valid nonces): 0 kH/s
  Hashrate (accepted shares): 0 kH/s
FPGA 1:
  Accepted: 0
  Rejected: 0 (0.00%)
  Invalid: 0 (0.00%)
  Hashrate (all nonces): 0 kH/s
  Hashrate (valid nonces): 0 kH/s
  Hashrate (accepted shares): 0 kH/s
Total hashrate for device: 0 kH/s / 0 kH/s / 0 kH/s

atavacron

full member

Activity: 224

Merit: 100

The definition of insanity is doing the same thing

Quote from: kramble on October 29, 2013, 09:02:12 AM

Quote from: atavacron on October 29, 2013, 08:52:40 AM

OK. I'm running overclock'd right now.

Wow, 7k diff.

Cheers. The new build is done (sometimes it can go quickly) ...

https://www.dropbox.com/s/77wg1smijyfpvx3/X6500-Robust-v03-2core-fmax-60MHz.bit

The timing report gives 71MHz as max speed, so in practice you may get 90-100MHz out of it (still well below the 200MHz for my current lancelot build, but its still somewhere around 400Mhash/s for the pair of devices). Just going to start off a 100Mhz build now (this will probably take much longer as its well above the 71MHz initial max, perhaps I'll just do a 80Mhz one first).

Let me know if the new build works (I may well have introduced some bugs with the multicore port).

Got it. Testing now.

kramble

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Activity: 384

Merit: 250

Quote from: atavacron on October 29, 2013, 08:52:40 AM

OK. I'm running overclock'd right now.

Wow, 7k diff.

Cheers. The new build is done (sometimes it can go quickly) ...

https://www.dropbox.com/s/77wg1smijyfpvx3/X6500-Robust-v03-2core-fmax-60MHz.bit

The timing report gives 71MHz as max speed, so in practice you may get 90-100MHz out of it (still well below the 200MHz for my current lancelot build, but its still somewhere around 400Mhash/s for the pair of devices). Just going to start off a 100Mhz build now (this will probably take much longer as its well above the 71MHz initial max, perhaps I'll just do a 80Mhz one first).

Let me know if the new build works (I may well have introduced some bugs with the multicore port).

atavacron

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Activity: 224

Merit: 100

The definition of insanity is doing the same thing

Quote from: kramble on October 29, 2013, 08:34:13 AM

Quote from: atavacron on October 29, 2013, 08:12:08 AM

Awesome!!!
I'll be available most of the day (EST) if you want me to test further changes.

I'm currently building a 2 core version, but it can take several hours (the xilinx tools are a real PITA, place & route is pretty much a lottery as to how well it proceeds). I'll let you know when the first one is done (its just a slow 60MHz build for now as that gives the best chance of a quick result).

In the meantime you could give the overclocking a try, it will be useful to see how fast it will clock. Then just let it hash, perhaps you'll get a block (though at the current 7k difficulty that may take a while) Cool

OK. I'm running overclock'd right now.

Wow, 7k diff.

kramble

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Activity: 384

Merit: 250

Quote from: atavacron on October 29, 2013, 08:12:08 AM

Awesome!!!
I'll be available most of the day (EST) if you want me to test further changes.

I'm currently building a 2 core version, but it can take several hours (the xilinx tools are a real PITA, place & route is pretty much a lottery as to how well it proceeds). I'll let you know when the first one is done (its just a slow 60MHz build for now as that gives the best chance of a quick result).

In the meantime you could give the overclocking a try, it will be useful to see how fast it will clock. Then just let it hash, perhaps you'll get a block (though at the current 7k difficulty that may take a while) Cool

atavacron

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Activity: 224

Merit: 100

The definition of insanity is doing the same thing

Quote from: kramble on October 29, 2013, 03:13:34 AM

Quote from: atavacron on October 28, 2013, 11:23:27 PM

Well, it seems to be doing something interesting. I've got rejects.

I loaded "X6500-Robust-v02-fmax-100MHz.bit" with x6500-miner and ran the miner. Below is the a clip of the output prior to and including the program exit.

"X6500-Robust-v02-fmax-150MHz.bit" would load but sat idle when using the miner.

Great! Its working fine. The hashes are valid (eight trailing zeros, difficulty 1), so you just need to wait until it finds one that's less than the network difficulty and you've got yourself a block. In explaination, the fpga miner returns difficulty one hashes (just like in bitcoin). If you were mining against a pool these would all be credited as shares, but since you're solo mining they will (almost) all be rejected. However you will need to wait a long time for a block at those hash rates, eg ...
[6 accepted, 15215 failed] from my current log (been running around 24 hours).

You could try pushing up the clock rate using the --overclock argument, just increase it until you get a significant number of invalid hashes (anything that does NOT have eight trailing zeros), then back it off a bit. You can comment out the midstatehex print at line 358 of fpga.py if this is annoying (its just there for debugging.

It is rather strange than the 150MHz build does not work, as it should still boot up at 50MHz and the initial overclock should not affect the JTAG/DCM. Must be some weird failure mode. Anyway now we know the basic code works I'll do some more builds to add in the second core and the output FIFO. Then its just a matter of testing each variant to see what works and what doesn't. Should eventually get the hash rate up towards that goal of 800Mhash/sec for the pair of fpgas Cheesy

Awesome!!!

I'll be available most of the day (EST) if you want me to test further changes.

kramble

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Activity: 384

Merit: 250

Quote from: atavacron on October 28, 2013, 11:23:27 PM

Well, it seems to be doing something interesting. I've got rejects.

I loaded "X6500-Robust-v02-fmax-100MHz.bit" with x6500-miner and ran the miner. Below is the a clip of the output prior to and including the program exit.

"X6500-Robust-v02-fmax-150MHz.bit" would load but sat idle when using the miner.

Great! Its working fine. The hashes are valid (eight trailing zeros, difficulty 1), so you just need to wait until it finds one that's less than the network difficulty and you've got yourself a block. In explaination, the fpga miner returns difficulty one hashes (just like in bitcoin). If you were mining against a pool these would all be credited as shares, but since you're solo mining they will (almost) all be rejected. However you will need to wait a long time for a block at those hash rates, eg ...
[6 accepted, 15215 failed] from my current log (been running around 24 hours).

You could try pushing up the clock rate using the --overclock argument, just increase it until you get a significant number of invalid hashes (anything that does NOT have eight trailing zeros), then back it off a bit. You can comment out the midstatehex print at line 358 of fpga.py if this is annoying (its just there for debugging.

It is rather strange than the 150MHz build does not work, as it should still boot up at 50MHz and the initial overclock should not affect the JTAG/DCM. Must be some weird failure mode. Anyway now we know the basic code works I'll do some more builds to add in the second core and the output FIFO. Then its just a matter of testing each variant to see what works and what doesn't. Should eventually get the hash rate up towards that goal of 800Mhash/sec for the pair of fpgas Cheesy

atavacron

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Activity: 224

Merit: 100

The definition of insanity is doing the same thing

Quote from: kramble on October 28, 2013, 01:54:45 PM

Quote from: atavacron on October 28, 2013, 08:14:39 AM

I'll be AFK for some time at work. I'll check back with you as soon as I return home.

New version is now up https://github.com/kramble/FPGA-Blakecoin-Miner/tree/master/experimental/X6500-Robust

Bitstreams (same code, just different initial DCM synthesis clock) ...

https://www.dropbox.com/s/58bkb5k4ts8k7j1/X6500-Robust-v02-fmax-100MHz.bit
https://www.dropbox.com/s/lygc90a0xz9el4q/X6500-Robust-v02-fmax-150MHz.bit

Try them both, its possible the faster one was causing problems before.

Since I removed the output FIFO I took the time to do some simulation of the jtag_comm, so hopefully this will work. If not then I'm going to have to do a build for the Lancelot and debug the JTAG I/O with that. I expect this will take some significant time.

Well, it seems to be doing something interesting. I've got rejects.

I loaded "X6500-Robust-v02-fmax-100MHz.bit" with x6500-miner and ran the miner. Below is the a clip of the output prior to and including the program exit.

"X6500-Robust-v02-fmax-150MHz.bit" would load but sat idle when using the miner.

Code:

hash cbbc7c728d2c30660a37dae6e6363caa0cb3929466a327ceb3c811ac00000000
2013-10-29 00:10:27 | rejected 37c6d309
0 kH/s | 0/5/0 100.00%/0.00%midstatehex= 178f52078ab83a108e0303f153ac22018a9cb00fe3d7d48d12eb1aa8c2e99310
midstatehex= c555571b3acf3a6203b8ffabd6b7c195caf2e242888239e9f8fd51a0eb4b99de
0 kH/s | 0/5/0 100.00%/0.00%hrnonce= e0f3da0e
hash f2ccafb0ce960609f78b1d85966f1d0a922ac13d731e6d12b51a7cd600000000
2013-10-29 00:10:35 | rejected edaf3e0
0 kH/s | 0/6/0 100.00%/0.00%midstatehex= 8e90b7bf6520b2fb0ebef042aaffa274677b03ed17915a979822bbec663f52bf
midstatehex= 98c2d76b50e9d5ebefee845c66a606137a3d18f65684cbc1318c95e4b0ab2979
0 kH/s | 0/6/0 100.00%/0.00%hrnonce= 13c5b612
hash 779615cc24e81a7f836954f5bd5a45efe4efbe3a7a05bc0cac02099800000000
2013-10-29 00:10:58 | rejected 12b6c513
0 kH/s | 0/7/0 100.00%/0.00%midstatehex= bbd55aa308f3dd6f607aa8d4ec23948121395bab3f4b06c6ce484611f433d06b
midstatehex= 96b5c3359fc7b9f6498e670d31e0fdf3c1a3f2a2235cb210fbea27a7a2b64c48
0 kH/s | 0/7/0 100.00%/0.00%midstatehex= 0b67fbdf3761c5f5ca752ba1fd1abc7e549ac481c12c7607ea694448bd10554a
midstatehex= c498a5ff5d05af0ee06f62d9152887e936f78859d2e514108a7c444b7bab681b
2013-10-29 00:11:39 | Exiting...

Run Summary:
-------------
Device: 0
Serial: A5VNUHQI
Number of FPGAs: 2
Running time: 5m26s
Getwork interval: 20 secs
FPGA 0:
Accepted: 0
Rejected: 3 (100.00%)
Invalid: 0 (0.00%)
Hashrate (all nonces): 39.45 MH/s
Hashrate (valid nonces): 0 kH/s
Hashrate (accepted shares): 0 kH/s
FPGA 1:
Accepted: 0
Rejected: 4 (100.00%)
Invalid: 0 (0.00%)
Hashrate (all nonces): 52.60 MH/s
Hashrate (valid nonces): 0 kH/s
Hashrate (accepted shares): 0 kH/s
Total hashrate for device: 92.05 MH/s / 0 kH/s / 0 kH/s

kramble

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Activity: 384

Merit: 250

Quote from: atavacron on October 28, 2013, 08:14:39 AM

I'll be AFK for some time at work. I'll check back with you as soon as I return home.

New version is now up https://github.com/kramble/FPGA-Blakecoin-Miner/tree/master/experimental/X6500-Robust

Bitstreams (same code, just different initial DCM synthesis clock) ...

https://www.dropbox.com/s/58bkb5k4ts8k7j1/X6500-Robust-v02-fmax-100MHz.bit
https://www.dropbox.com/s/lygc90a0xz9el4q/X6500-Robust-v02-fmax-150MHz.bit

Try them both, its possible the faster one was causing problems before.

Since I removed the output FIFO I took the time to do some simulation of the jtag_comm, so hopefully this will work. If not then I'm going to have to do a build for the Lancelot and debug the JTAG I/O with that. I expect this will take some significant time.

atavacron

full member

Activity: 224

Merit: 100

The definition of insanity is doing the same thing

Quote from: kramble on October 28, 2013, 05:12:57 AM

Quote from: atavacron on October 27, 2013, 07:38:56 PM

There are three LEDs on the board, one at the power input and two at the far sides of the FPGAs with the label "Done". At power on the two "Done" LEDs are off. However, there turn on just after loading the bitstream.

Unfortunately DONE is a dedicated configuration pin, not user drivable, but it is useful as it tells us the bitstream has been successfully loaded. Here is the (simplified) schematic.

Just starting on the robustified version (I'll take out the results FIFO too as that's a black-box NGC file which could be an issue due to different versions of ISE). Should be done sometime later today.

Ah, I see. At least the LEDs are of some use.

I'll be AFK for some time at work. I'll check back with you as soon as I return home.

SpeedDemon13

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Activity: 518

Merit: 500

kramble

sr. member

Activity: 384

Merit: 250

Quote from: atavacron on October 27, 2013, 07:38:56 PM

There are three LEDs on the board, one at the power input and two at the far sides of the FPGAs with the label "Done". At power on the two "Done" LEDs are off. However, there turn on just after loading the bitstream.

Unfortunately DONE is a dedicated configuration pin, not user drivable, but it is useful as it tells us the bitstream has been successfully loaded. Here is the (simplified) schematic.

Just starting on the robustified version (I'll take out the results FIFO too as that's a black-box NGC file which could be an issue due to different versions of ISE). Should be done sometime later today.

mogrith

legendary

Activity: 1470

Merit: 1001

Use Coinbase Account almosanywhere with Shift card

Pool will be nice dif is rising. Which is good as it means lots of miners ( or at least lots of MH/s).

I'm happier getting 5 coins every hour than 50 coins every 10 hrs even if it the same amount over time.

Vorksholk

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Merit: 1029