Monero community could be vibrant, but good question is why the monero devs didnt increased the scratchpad size from the current size (2Mb), fpga miners are not affected by this fork
I talked to another cryptonight coin developer about fpga, he said that it's cost prohibitive due to memory restrictions. So there goes fpga out the door, cause I was thinking fpga too.
I'm developing many algorithms for the Virtex Ultrascale+ VU9P on the VCU1525 board and this FPGA has 47MB of internal SRAM, enough for 22 instances of Cryptonight V7. Your developer friend is gravely mistaken.
Having said that, Cryptonight V7 is not the most profitable algorithm for FPGA's at the moment, but high end FPGA's always beat GPU's, and ROI for the high end FPGA's are around 50-110 days vs. years for GPU's.
I will be releasing my bitstreams (to the public) soon, my current plan is to release them for free with a 4% mining fee. And you would need to buy your own FPGA boards from Avnet/Digikey/Xilinx/Digilent/Hitechglobal/Bittware, etc...
Amazing. Can't wait for that. Do you have an estimated date?
First public-ready algorithms should be done around mid to late June. However I am hesitant to 'release' the bitstreams unless numerous algorithms are available. I wouldn't want someone to invest $10K in hardware with only 1 or 2 algorithms in case those coins profit or ROI suddenly changes. A good investment would be to have 4-5 algorithms available, making the hardware more secure against market changes.
Anyway, once people start mining with PC's linked to numerous high end FPGA cards, they will be 'immune' to forks since the algorithms in the FPGA's can be changed as fast as developers can fork their coin, actually faster in most cases since even a poorly tested rig can still mine, whereas a coin cannot fork until the new setup is heavily tested.
Thank you for the amazing work you have been doing with FPGAs. I truly respect you for pushing the boundaries of today's mining knowledge.
So let's say that FPGAs turn out to be a healthy and profitable substitution to GPUs as we hope, so far Cryptonight is the only algo that was able to put ASICs out of the game for a while, this being said, won't ASICs just be developed for the remaining algos, beating FPGAs at what they can do best?
If so this leaves me thinking that FPGAs profitable work could then be allocated to Cryptonight, which is ASIC resistant as we speak, but as you have stated yourselfthis algo implementation is not the best mining use case for FPGAs and at that point once more accessible FPGA mining solutions are released and more FPGA hardware is purchased won't that put us back where things are now?