Topic: BFL ASIC specifications - page 2. (Read 4273 times)

Quote from: J35st3r on June 08, 2013, 03:53:11 PM

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalksearch.org/topic/wild-and-unsubstantiated-speculation-about-bfls-power-woes-166321

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics. In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink. This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops. If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C. In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Of course one defect in a pipeline wrecks the pipeline. Sorry if I assumed it was obvious, but it is. However, for such a high defect per area density, modern commercial CPU and GPU manufacture would be lucky to yield one working chip per 300mm wafer. GPU's would cost > 10k USD.

I was just reverse engineering the 7950/7970 die size (352mm2) with their binning. Roughly 45x the die size and they disable 256 of the cores during binning. It didn't seem unlikely that 50-100 of those cores underperform or fail tests. But I was just doing back of the envelope calculations. I might be able to lay my hands on what sort of defect rate AMD actually sees at that die size and what their worst case scenario looks like.

Might be interesting for comparison purposes, but I realize a GPU of that size is a "whole nother critter". Grin

ultrix

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If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalksearch.org/topic/m.2408299

Personally I think rolled cores are a wise decision as he should yield slightly less performance per area assuming ideal situations and higher when defects are throw into the equation. The advantages of constant folding for the ternary addition required for SHA256 are relatively minimal when you leave the realm of FPGAs/structured ASICs. ASIC perf/cost centers around usable area at the end of the day. That is unless your goal is to make some really fancy glass.

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Quote from: k9quaint on June 08, 2013, 04:05:05 PM

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalksearch.org/topic/wild-and-unsubstantiated-speculation-about-bfls-power-woes-166321

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics. In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink. This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops. If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C. In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Of course one defect in a pipeline wrecks the pipeline. Sorry if I assumed it was obvious, but it is. However, for such a high defect per area density, modern commercial CPU and GPU manufacture would be lucky to yield one working chip per 300mm wafer. GPU's would cost > 10k USD.

J35st3r

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Bitfury's method is a lot more resistant to failure. If you lose a few cores out of 756, nobody cares. Just have the firmware test em on initial and mark em dead if they don't test right.

I don't think he does (the comms protocol seems pretty basic). But you probably don't have to as bad cores will mostly just produce bad hashes, which can just be filtered out in the mining software (I assume the current miners check the nonces before submitting them to a pool, its a low cost operation to do just for the winning shares).

k9quaint

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Quote from: J35st3r on June 08, 2013, 03:53:11 PM

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalksearch.org/topic/m.2408299

0.5 (mm2) is still a lot of real estate you need to get perfect in order for 1 engine to function. It might stretch the boundaries of the process.
Bitfury's method is a lot more resistant to failure. If you lose a few cores out of 756, nobody cares. Just have the firmware test em on initial and mark em dead if they don't test right.

J35st3r

full member

Activity: 196

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If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

Good point, though yields still should not be that crappy. Interestingly Bitfury's new chip is using 756 rolled double-cores https://bitcointalksearch.org/topic/m.2408299

k9quaint

legendary

Activity: 1190

Merit: 1000

Do you care to speculate what could be the specific mistake that the BFL's designers made?

For example eldentyrell speculated a while back that they made their simulations at the default temperature chosen by SPICE in absence of specific setting: 25 deg C.

https://bitcointalksearch.org/topic/wild-and-unsubstantiated-speculation-about-bfls-power-woes-166321

Obviously, we don't have sufficient information to make a real assesment; but I think even making a scientific wild ass guess will have some educational value for the readership of this forum.

I would guess that when doing integrity simulations they did not set the upper bound to say 85C, which is fairly common in commercial electronics. In applications that use heatsinks sometimes this results in incorrectly calculating the efficiency of said heatsink. This can be empirically tested, say by cooling with LN2, which is readily available at most lab test supply shops. If the chip error rate reduces at the same clock frequency, then the efficiency of the heatsink and/or upper bound of simulation was not 85C. In Cadence's package design software and subsequent sim, -20C and 85C are used as the lower and upper bounds, respectively.

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

If they used fully unrolled SHA256 pipelines (128+ stages), a single glitch anywhere would take out an entire engine. If each engine takes up 0.5mm and one glitch would wreck it, that could explain crappy yields.

J35st3r

full member

Activity: 196

Merit: 100

There are a number of other reasons they could be experiencing low yields, but the facts are a) Global Foundaries' 65nm process is fairly mature b) the design rule checks (DRC's) provided by foundaries and/or built into any usable EDA software would catch the majority of other potential culprits, such as signal integrity or cross talk issues.

Agreed, insanely low yields, plus several design iterations suggests incompetent development engineers. Also this:

Quote

Chip grades: Chips come in four grades of performance. Chips are sold in mixed grade lots. A grade has 16 engines, B grade has 15 engines, C grade has 14 engines and D grade has no less than 12 engines. All chips run at a minimum of 250 mhz. Higher grade chips will run up to 294mhz. The percentage distribution in each lot is 60% Grade A, 20% Grade B, 15% Grade C and 5% Grade D

I've been out of the biz a long time now, but why the claim that perfect chips clock faster than defective chips? I suppose they could be accounting for parasitic power consumption of defective cores limiting the clock rate to keep power dissipation down, but then what are they going to do with the <250MHz parts? And have they fully characterised their dodgy design? It would be embarrassing if the yield/speed varies hugely between batches. Oh and up to, I always mentally translate that as less than.

ultrix

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